LMK03033 Series

1843 to 2160-MHz, 800-fs RMS jitter, precision clock conditioner with integrated VCO

Catalog

1843 to 2160-MHz, 800-fs RMS jitter, precision clock conditioner with integrated VCO

Part	Package / Case	Mounting Type	Frequency - Max [Max]	Number of Circuits	Supplier Device Package	Input	Output	Operating Temperature [Max]	Operating Temperature [Min]	Type	Divider/Multiplier	Ratio - Input:Output	Voltage - Supply [Max]	Voltage - Supply [Min]	Function	Utilized IC / Part	Supplied Contents	Primary Attributes	Contents
Texas Instruments LMK03033CISQ/NOPB	48-WFQFN Exposed Pad	Surface Mount	2.16 GHz	1	48-WQFN (7x7)	LVCMOS LVDS LVPECL	LVDS LVPECL	85 °C	-40 °C	Clock Conditioner	Yes/No	1:8	3.45 V	3.15 V
Texas Instruments LMK03033ISQE/NOPB	48-WFQFN Exposed Pad	Surface Mount	2.16 GHz	1	48-WQFN (7x7)	LVCMOS LVDS LVPECL	LVDS LVPECL	85 °C	-40 °C	Clock Conditioner	Yes/No	1:8	3.45 V	3.15 V
Texas Instruments LMK03033CISQE/NOPB	48-WFQFN Exposed Pad	Surface Mount	2.16 GHz	1	48-WQFN (7x7)	LVCMOS LVDS LVPECL	LVDS LVPECL	85 °C	-40 °C	Clock Conditioner	Yes/No	1:8	3.45 V	3.15 V
Texas Instruments LMK03033CEVAL										Timing					Clock Conditioner	LMK03033C	Board(s)	Jitter Cleaner	Board(s)
Texas Instruments LMK03033ISQ/NOPB	48-WFQFN Exposed Pad	Surface Mount	2.16 GHz	1	48-WQFN (7x7)	LVCMOS LVDS LVPECL	LVDS LVPECL	85 °C	-40 °C	Clock Conditioner	Yes/No	1:8	3.45 V	3.15 V
Texas Instruments LMK03033ISQX/NOPB	48-WFQFN Exposed Pad	Surface Mount	2.16 GHz	1	48-WQFN (7x7)	LVCMOS LVDS LVPECL	LVDS LVPECL	85 °C	-40 °C	Clock Conditioner	Yes/No	1:8	3.45 V	3.15 V

Catalog

1843 to 2160-MHz, 800-fs RMS jitter, precision clock conditioner with integrated VCO

Key Features

• Integrated VCO with Very Low Phase Noise FloorIntegrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/HzVCO Divider Values of 2 to 8 (All Divides)Channel Divider Values of 1, 2 to 510 (even divides)LVDS and LVPECL Clock OutputsPartially Integrated Loop FilterDedicated Divider and Delay Blocks on Each Clock OutputPin Compatible Family of Clocking Devices3.15 to 3.45 V OperationPackage: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a Clean Input ClockAll trademarks are the property of their respective owners.Integrated VCO with Very Low Phase Noise FloorIntegrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/HzVCO Divider Values of 2 to 8 (All Divides)Channel Divider Values of 1, 2 to 510 (even divides)LVDS and LVPECL Clock OutputsPartially Integrated Loop FilterDedicated Divider and Delay Blocks on Each Clock OutputPin Compatible Family of Clocking Devices3.15 to 3.45 V OperationPackage: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a Clean Input ClockAll trademarks are the property of their respective owners.

Description

The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations. The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO Divider to feed the various clock distribution blocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components. The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family. The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations. The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO Divider to feed the various clock distribution blocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components. The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family.