SN74LV6T14-EP Series

Enhanced-product six-bit inverting fixed-direction level translator with Schmitt-trigger inputs

Catalog

Enhanced-product six-bit inverting fixed-direction level translator with Schmitt-trigger inputs

Part	Logic Type	Input Logic Level - Low [Max]	Input Logic Level - Low [Min]	Voltage - Supply [Min]	Voltage - Supply [Max]	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case [custom]	Package / Case [custom]	Package / Case	Input Logic Level - High [Min]	Input Logic Level - High [Max]	Max Propagation Delay @ V, Max CL	Mounting Type	Supplier Device Package	Number of Circuits	Features	Number of Inputs	Current - Output High, Low [custom]	Current - Output High, Low [custom]
Texas Instruments SN74LV6T14PWREP	Inverter	1.075 V	0.685 V	1.6 V	5.5 V	125 °C	-40 °C	0.173 "	4.4 mm	14-TSSOP	1.2 V	2.03 V	12.5 ns	Surface Mount	14-TSSOP	6	Schmitt Trigger	6	8 mA	8 mA

Catalog

Enhanced-product six-bit inverting fixed-direction level translator with Schmitt-trigger inputs

Key Features

• Wide operating range of 1.8V to 5.5VSingle-supply voltage translator (refer to LVxT Enhanced Input Voltage):Up translation:1.2V to 1.8V1.5V to 2.5V1.8V to 3.3V3.3V to 5.0VDown translation:5.0V, 3.3V, 2.5V to 1.8V5.0V, 3.3V to 2.5V5.0V to 3.3V5.5V tolerant input pinsSupports standard pinoutsUp to 150Mbps with 5V or 3.3V VCCLatch-up performance exceeds 250mAper JESD 17Wide operating range of 1.8V to 5.5VSingle-supply voltage translator (refer to LVxT Enhanced Input Voltage):Up translation:1.2V to 1.8V1.5V to 2.5V1.8V to 3.3V3.3V to 5.0VDown translation:5.0V, 3.3V, 2.5V to 1.8V5.0V, 3.3V to 2.5V5.0V to 3.3V5.5V tolerant input pinsSupports standard pinoutsUp to 150Mbps with 5V or 3.3V VCCLatch-up performance exceeds 250mAper JESD 17

Description

The SN74LV6T14-EP device contains six independent Inverter with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8-V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output). The SN74LV6T14-EP device contains six independent Inverter with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8-V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).