LMK1D2102 Series

Dual bank 2-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer

Catalog

Dual bank 2-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer

Part	Ratio - Input:Output [custom]	Input	Output	Supplier Device Package	Frequency - Max [Max]	Voltage - Supply [Min]	Voltage - Supply [Max]	Mounting Type	Package / Case	Type	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Number of Circuits
Texas Instruments LMK1D2102RGTR	1:2	CML HCSL LVCMOS LVDS LVPECL	LVDS	16-VQFN (3x3)	2 GHz	1.71 V 2.375 V 3.135 V	1.89 V 2.625 V 3.465 V	Surface Mount	16-VFQFN Exposed Pad	Clock Buffer			105 °C	-40 °C	2

Catalog

Dual bank 2-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer

Key Features

• High-performance LVDS clock buffer family: up to 2 GHzDual 1:2 differential bufferDual 1:4 differential bufferSupply voltage: 1.71 V to 3.465 VFail-safe input operationLow additive jitter: < max 60 fs RMS in 12-kHz to 20-MHz @ 156.25 MHzVery low phase noise floor: -164 dBc/Hz (typical)Very low propagation delay < 575 ps maxOutput skew of 20 ps maxUniversal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels.LVDS reference voltage, VAC_REF, available for capacitive coupled inputsIndustrial temperature range: –40°C to 105°CPackaged inLMK1D2102: 3-mm x 3-mm, 16-Pin VQFNLMK1D2104: 5-mm x 5-mm, 28-Pin VQFNHigh-performance LVDS clock buffer family: up to 2 GHzDual 1:2 differential bufferDual 1:4 differential bufferSupply voltage: 1.71 V to 3.465 VFail-safe input operationLow additive jitter: < max 60 fs RMS in 12-kHz to 20-MHz @ 156.25 MHzVery low phase noise floor: -164 dBc/Hz (typical)Very low propagation delay < 575 ps maxOutput skew of 20 ps maxUniversal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels.LVDS reference voltage, VAC_REF, available for capacitive coupled inputsIndustrial temperature range: –40°C to 105°CPackaged inLMK1D2102: 3-mm x 3-mm, 16-Pin VQFNLMK1D2104: 5-mm x 5-mm, 28-Pin VQFN

Description

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of up to 8 pairs of differential LVDS clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input and up to 4 LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML or LVCMOS. The LMK1D210x is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage as shown in Figure 9-6 must be applied to the unused negative input pin. Using the control pin (EN), output banks can either be enabled or disabled. If this pin is left open, two buffers with all outputs are enabled, if switched to a logic "0", both banks with all outputs are disabled (static logic "0"), if switched to a logic "1", one bank and its outputs are disabled while another bank with its outputs are enabled. The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal. The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature). The LMK1D210x package variant is shown in the table below: The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of up to 8 pairs of differential LVDS clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input and up to 4 LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML or LVCMOS. The LMK1D210x is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage as shown in Figure 9-6 must be applied to the unused negative input pin. Using the control pin (EN), output banks can either be enabled or disabled. If this pin is left open, two buffers with all outputs are enabled, if switched to a logic "0", both banks with all outputs are disabled (static logic "0"), if switched to a logic "1", one bank and its outputs are disabled while another bank with its outputs are enabled. The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal. The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature). The LMK1D210x package variant is shown in the table below: