SN74LV4T08-Q1 Series

Automotive single power supply quadruple AND gates with logic level shifter

Catalog

Automotive single power supply quadruple AND gates with logic level shifter

Part	Input Logic Level - Low [Max]	Input Logic Level - Low [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Input Logic Level - High [Max]	Input Logic Level - High [Min]	Supplier Device Package	Number of Inputs	Number of Circuits	Logic Type	Grade	Voltage - Supply [Min]	Voltage - Supply [Max]	Features	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Qualification	Package / Case [custom]	Package / Case [custom]	Package / Case
Texas Instruments SN74LV4T08QPWRQ1	0.85 V	0.5 V	8 mA	8 mA	2 V	1.1 V	14-TSSOP	2	4	AND Gate	Automotive	1.6 V	5.5 V	Schmitt Trigger	125 °C	-40 °C	Surface Mount	AEC-Q100	0.173 "	4.4 mm	14-TSSOP
Texas Instruments SN74LV4T08QWBQARQ1	0.85 V	0.5 V	8 mA	8 mA	2 V	1.1 V	14-WQFN (3x2.5)	2	4	AND Gate	Automotive	1.6 V	5.5 V	Schmitt Trigger	125 °C	-40 °C	Surface Mount	AEC-Q100			14-WFQFN Exposed Pad

Catalog

Automotive single power supply quadruple AND gates with logic level shifter

Key Features

• AEC-Q100 qualified for automotive applications:Device temperature grade 1: -40°C to +125°CDevice HBM ESD classification level 2Device CDM ESD classification level C4BAvailable in wettable flank QFN (WBQA) packageWide operating range of 1.8 V to 5.5 VSingle-supply voltage translator (refer to LVxT Enhanced Input Voltage):Up translation:1.2 V to 1.8 V1.5 V to 2.5 V1.8 V to 3.3 V3.3 V to 5.0 VDown translation:5.0 V, 3.3 V, 2.5 V to 1.8 V5.0 V, 3.3 V to 2.5 V5.0 V to 3.3 V5.5-V tolerant input pinsSupports standard pinoutsUp to 150 Mbps with 5-V or 3.3-V V CCLatch-up performance exceeds 250 mA per JESD 17AEC-Q100 qualified for automotive applications:Device temperature grade 1: -40°C to +125°CDevice HBM ESD classification level 2Device CDM ESD classification level C4BAvailable in wettable flank QFN (WBQA) packageWide operating range of 1.8 V to 5.5 VSingle-supply voltage translator (refer to LVxT Enhanced Input Voltage):Up translation:1.2 V to 1.8 V1.5 V to 2.5 V1.8 V to 3.3 V3.3 V to 5.0 VDown translation:5.0 V, 3.3 V, 2.5 V to 1.8 V5.0 V, 3.3 V to 2.5 V5.0 V to 3.3 V5.5-V tolerant input pinsSupports standard pinoutsUp to 150 Mbps with 5-V or 3.3-V V CCLatch-up performance exceeds 250 mA per JESD 17

Description

The SN74LV4T08-Q1 contains four independent 2-input AND Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output). The SN74LV4T08-Q1 contains four independent 2-input AND Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).