AFE5401-Q1 Series

Quad-Channel Integrated Analog Front End for Automotive Radar

Catalog

Quad-Channel Integrated Analog Front End for Automotive Radar

Part	Number of Bits	Qualification	Package / Case	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Grade	Power (Watts)	Number of Channels	Mounting Type	Supplier Device Package	Voltage - Supply, Analog
Texas Instruments AFE5401TRGCRQ1	12 bits	AEC-Q100	64-VFQFN Exposed Pad	1.8 V	3.3 V	Automotive	64 mW	4	Surface Mount	64-VQFN (9x9)
Texas Instruments AFE5401TRGCTQ1	12 bits	AEC-Q100	64-VFQFN Exposed Pad			Automotive	64 mW	4	Surface Mount	64-VQFN (9x9)	1.8 V 3.3 V

Catalog

Quad-Channel Integrated Analog Front End for Automotive Radar

Key Features

• Qualified for Automotive ApplicationsAEC-Q100 Qualified With the Following Results:Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature RangeDevice HBM ESD Classification Level 2Device CDM ESD Classification Level C4BIntegrated Analog Front-End Includes:Quad LNA, Equalizer, PGA, Antialiasing Filter, and ADCInput-Referred Noise with 30-dB PGA Gain:2.9-nV/√Hzfor 15-dB LNA Gain2.0-nV/√Hzfor 18-dB LNA Gain with HIGH_POW_LNA ModeSimultaneous Sampling Across ChannelsProgrammable LNA Gain:12 dB, 15 dB, 16.5 dB, and 18 dBProgrammable Equalizer ModesBuilt-In Diagnostic ModesTemperature SensorProgrammable-Gain Amplifiers (PGAs):0 dB to 30 dB in 3-dB StepsProgrammable, Third-Order, Antialiasing Filter:7 MHz, 8 MHz, 10.5 MHz, and 12 MHzAnalog-to-Digital Converter (ADC):Quad Channel, 12 Bits, 25 MSPS per ChannelNo External Decoupling Required for ReferencesParallel CMOS Outputs64-mW Total Core Power per Channel at25 MSPS per ChannelSupplies: 1.8 V and 3.3 VPackage: 9-mm × 9-mm VQFN-64Qualified for Automotive ApplicationsAEC-Q100 Qualified With the Following Results:Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature RangeDevice HBM ESD Classification Level 2Device CDM ESD Classification Level C4BIntegrated Analog Front-End Includes:Quad LNA, Equalizer, PGA, Antialiasing Filter, and ADCInput-Referred Noise with 30-dB PGA Gain:2.9-nV/√Hzfor 15-dB LNA Gain2.0-nV/√Hzfor 18-dB LNA Gain with HIGH_POW_LNA ModeSimultaneous Sampling Across ChannelsProgrammable LNA Gain:12 dB, 15 dB, 16.5 dB, and 18 dBProgrammable Equalizer ModesBuilt-In Diagnostic ModesTemperature SensorProgrammable-Gain Amplifiers (PGAs):0 dB to 30 dB in 3-dB StepsProgrammable, Third-Order, Antialiasing Filter:7 MHz, 8 MHz, 10.5 MHz, and 12 MHzAnalog-to-Digital Converter (ADC):Quad Channel, 12 Bits, 25 MSPS per ChannelNo External Decoupling Required for ReferencesParallel CMOS Outputs64-mW Total Core Power per Channel at25 MSPS per ChannelSupplies: 1.8 V and 3.3 VPackage: 9-mm × 9-mm VQFN-64

Description

The AFE5401-Q1 is an analog front-end (AFE), targeting applications where the level of integration is critical. The device includes four channels, with each channel comprising a low-noise amplifier (LNA), a programmable equalizer (EQ), a programmable gain amplifier (PGA), and an antialias filter followed by a high-speed, 12-bit, analog-to-digital converter (ADC) at 25 MSPS per channel. Each of the four differential input pairs are amplified by an LNA and are followed by a PGA with a programmable gain range from 0 dB to 30 dB. An antialias, low-pass filter (LPF) is also integrated between the PGA and ADC for each channel. Each LNA, PGA, and antialiasing filter output is differential (limited to 2 VPP). The antialiasing filter drives the on-chip, 12-bit, 25-MSPS ADC. The four ADC outputs are multiplexed on a 12-bit, parallel, CMOS output bus. The device is available in a 9-mm × 9-mm, VQFN-64 package and is specified over a temperature range of –40°C to +105°C. For more information, contactAFE5401_info@list.ti.com. The AFE5401-Q1 is an analog front-end (AFE), targeting applications where the level of integration is critical. The device includes four channels, with each channel comprising a low-noise amplifier (LNA), a programmable equalizer (EQ), a programmable gain amplifier (PGA), and an antialias filter followed by a high-speed, 12-bit, analog-to-digital converter (ADC) at 25 MSPS per channel. Each of the four differential input pairs are amplified by an LNA and are followed by a PGA with a programmable gain range from 0 dB to 30 dB. An antialias, low-pass filter (LPF) is also integrated between the PGA and ADC for each channel. Each LNA, PGA, and antialiasing filter output is differential (limited to 2 VPP). The antialiasing filter drives the on-chip, 12-bit, 25-MSPS ADC. The four ADC outputs are multiplexed on a 12-bit, parallel, CMOS output bus. The device is available in a 9-mm × 9-mm, VQFN-64 package and is specified over a temperature range of –40°C to +105°C. For more information, contactAFE5401_info@list.ti.com.