DIX4192-Q1 Series
Automotive Integrated Digital Audio Interface Receiver and Transmitter
Manufacturer: Texas Instruments
Catalog
Automotive Integrated Digital Audio Interface Receiver and Transmitter
Key Features
• Qualified for Automotive ApplicationsAEC-Q100 Qualified With the Following Results:Device Temperature Grade:DIX4192I-Q1: Grade 3 (–40°C to +85°C)DIX4192T-Q1: Grade 2 (–40°C to +105°C)Device HBM ESD Classification Level 2Device CDM ESD Classification Level C4BDigital Audio Interface Transmitter (DIT)PCM/Encoded data to S/PDIF ConversionSupports Sampling Rates Up to 216 kHzIncludes Differential Line Driver andCMOS-Buffered OutputsDigital Audio Interface Receiver (DIR)S/PDIF to Stereo PCM Conversion / Encoded dataPLL Lock Range Includes Sampling Rates from 20 kHz to 216 kHzFour Differential-Input Line Receivers and an Input MultiplexerBypass Multiplexer Routes Line Receiver Outputs to Line Driver and Buffer OutputsAutomatic Detection of Non-PCM Audio Streams (DTS CD/LD and IEC 61937 formats)Audio CD Q-Channel Sub-Code Decoding and Data BufferLow Jitter Recovered Clock OutputUser-Selectable Serial Host Interface: SPI™ or I2CProvides Access to On-Chip Registers and Data BuffersStatus Registers and Interrupt Generation for Flag and Error ConditionsBlock-Sized Data Buffers for Both Channel Status and User DataTwo Audio Serial Ports (Ports A and B)Synchronous Serial Interface to External Signal Processors, Data Converters, and LogicSlave or Master Mode Operation With Sampling Rates Up to 216 kHzSupports Left-Justified, Right-Justified, and Philips I2S™ Data FormatsSupports Audio Data Word Lengths Up to24 BitsFour General-Purpose Digital OutputsMultifunction Programmable Through Control RegistersExtensive Power-Down SupportFunctional Blocks May Be Disabled Individually When Not In UseOperates From 1.8-V Core and 3.3-V I/O Power SuppliesSmall TQFP-48 Package, Compatible With theSRC4382andSRC4392Qualified for Automotive ApplicationsAEC-Q100 Qualified With the Following Results:Device Temperature Grade:DIX4192I-Q1: Grade 3 (–40°C to +85°C)DIX4192T-Q1: Grade 2 (–40°C to +105°C)Device HBM ESD Classification Level 2Device CDM ESD Classification Level C4BDigital Audio Interface Transmitter (DIT)PCM/Encoded data to S/PDIF ConversionSupports Sampling Rates Up to 216 kHzIncludes Differential Line Driver andCMOS-Buffered OutputsDigital Audio Interface Receiver (DIR)S/PDIF to Stereo PCM Conversion / Encoded dataPLL Lock Range Includes Sampling Rates from 20 kHz to 216 kHzFour Differential-Input Line Receivers and an Input MultiplexerBypass Multiplexer Routes Line Receiver Outputs to Line Driver and Buffer OutputsAutomatic Detection of Non-PCM Audio Streams (DTS CD/LD and IEC 61937 formats)Audio CD Q-Channel Sub-Code Decoding and Data BufferLow Jitter Recovered Clock OutputUser-Selectable Serial Host Interface: SPI™ or I2CProvides Access to On-Chip Registers and Data BuffersStatus Registers and Interrupt Generation for Flag and Error ConditionsBlock-Sized Data Buffers for Both Channel Status and User DataTwo Audio Serial Ports (Ports A and B)Synchronous Serial Interface to External Signal Processors, Data Converters, and LogicSlave or Master Mode Operation With Sampling Rates Up to 216 kHzSupports Left-Justified, Right-Justified, and Philips I2S™ Data FormatsSupports Audio Data Word Lengths Up to24 BitsFour General-Purpose Digital OutputsMultifunction Programmable Through Control RegistersExtensive Power-Down SupportFunctional Blocks May Be Disabled Individually When Not In UseOperates From 1.8-V Core and 3.3-V I/O Power SuppliesSmall TQFP-48 Package, Compatible With theSRC4382andSRC4392
Description
AI
The DIX4192-Q1 device is a highly-integrated CMOS device designed for use in professional and broadcast digital audio systems. The DIX4192-Q1 combines a digital audio interface receiver (DIR) and transmitter (DIT), two audio serial ports, and flexible distribution logic for interconnection of the function block data and clocks.
The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201 interface standards. The audio serial ports and DIT may be operated at sampling rates up to 216 kHz. The DIR lock range includes sampling rates from 20 kHz to 216 kHz.
The DIX4192-Q1 device is configured using on-chip control registers and data buffers, which are accessed through either a four-wire serial peripheral interface (SPI) port, or a two-wire I2C bus interface. Status registers provide access to a variety of flag and error bits, which are derived from the various function blocks. An open-drain interrupt output pin is provided, and is supported by flexible interrupt reporting and mask options through control register settings. A master reset input pin is provided for initialization by a host processor or supervisory functions.
The DIX4192-Q1 device requires a 1.8-V core logic supply, in addition to a 3.3-V supply for powering portions of the DIR, DIT, and line driver and receiver functions. A separate logic I/O supply supports operation from 1.65 V to 3.6 V, providing compatibility with low-voltage logic interfaces typically found on digital signal processors and programmable logic devices.
The DIX4192-Q1 device is available in a lead-free, TQFP-48 package.
The DIX4192-Q1 device is a highly-integrated CMOS device designed for use in professional and broadcast digital audio systems. The DIX4192-Q1 combines a digital audio interface receiver (DIR) and transmitter (DIT), two audio serial ports, and flexible distribution logic for interconnection of the function block data and clocks.
The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201 interface standards. The audio serial ports and DIT may be operated at sampling rates up to 216 kHz. The DIR lock range includes sampling rates from 20 kHz to 216 kHz.
The DIX4192-Q1 device is configured using on-chip control registers and data buffers, which are accessed through either a four-wire serial peripheral interface (SPI) port, or a two-wire I2C bus interface. Status registers provide access to a variety of flag and error bits, which are derived from the various function blocks. An open-drain interrupt output pin is provided, and is supported by flexible interrupt reporting and mask options through control register settings. A master reset input pin is provided for initialization by a host processor or supervisory functions.
The DIX4192-Q1 device requires a 1.8-V core logic supply, in addition to a 3.3-V supply for powering portions of the DIR, DIT, and line driver and receiver functions. A separate logic I/O supply supports operation from 1.65 V to 3.6 V, providing compatibility with low-voltage logic interfaces typically found on digital signal processors and programmable logic devices.
The DIX4192-Q1 device is available in a lead-free, TQFP-48 package.
