ADC16DV160 Series
Dual-Channel, 16-Bit, 160-MSPS Analog-to-Digital Converter (ADC)
Manufacturer: Texas Instruments
Catalog
Dual-Channel, 16-Bit, 160-MSPS Analog-to-Digital Converter (ADC)
Key Features
• Low Power ConsumptionOn-Chip Precision Reference and Sample-and-Hold CircuitOn-Chip Automatic Calibration During Power-UpDual Data Rate LVDS Output PortDual Supplies: 1.8V and 3.0V OperationSelectable Input Range: 2.4 and 2.0 VPPSampling Edge Flipping with Clock Divider by 2 OptionInternal Clock Divide by 1 or 2On-Chip Low Jitter Duty-Cycle StabilizerPower-Down and Sleep ModesOutput Fixed Pattern GenerationOutput Clock Position Adjustment3-Wire SPIOffset Binary or 2's Complement Data Format68-Pin VQFN Package (10x10x0.8, 0.5mm Pin-Pitch)Key SpecificationsResolution: 16 BitsConversion Rate: 160 MSPSSNR (@FIN = 30 MHz): 78 dBFS (typ)SNR (@FIN = 197 MHz): 76 dBFS (typ)SFDR (@FIN = 30 MHz): 95 dBFS (typ)SFDR (@FIN = 197 MHz): 89 dBFS (typ)Full Power Bandwidth: 1.4 GHz (typ)Power Consumption:Core per channel: 612 mW (typ)LVDS Driver: 117 mW (typ)Total: 1.3W (typ)Operating Temperature Range (-40°C ~ 85°C)Low Power ConsumptionOn-Chip Precision Reference and Sample-and-Hold CircuitOn-Chip Automatic Calibration During Power-UpDual Data Rate LVDS Output PortDual Supplies: 1.8V and 3.0V OperationSelectable Input Range: 2.4 and 2.0 VPPSampling Edge Flipping with Clock Divider by 2 OptionInternal Clock Divide by 1 or 2On-Chip Low Jitter Duty-Cycle StabilizerPower-Down and Sleep ModesOutput Fixed Pattern GenerationOutput Clock Position Adjustment3-Wire SPIOffset Binary or 2's Complement Data Format68-Pin VQFN Package (10x10x0.8, 0.5mm Pin-Pitch)Key SpecificationsResolution: 16 BitsConversion Rate: 160 MSPSSNR (@FIN = 30 MHz): 78 dBFS (typ)SNR (@FIN = 197 MHz): 76 dBFS (typ)SFDR (@FIN = 30 MHz): 95 dBFS (typ)SFDR (@FIN = 197 MHz): 89 dBFS (typ)Full Power Bandwidth: 1.4 GHz (typ)Power Consumption:Core per channel: 612 mW (typ)LVDS Driver: 117 mW (typ)Total: 1.3W (typ)Operating Temperature Range (-40°C ~ 85°C)
Description
AI
The ADC16DV160 is a monolithic dual channel high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 160 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16DV160 can be re-calibrated at any time through the 3-wire Serial Peripheral Interface (SPI). An integrated low noise and stable voltage reference and differential reference buffer amplifier eases board level design. The on-chip duty cycle stabilizer with low additive jitter allows a wide range of input clock duty cycles without compromising dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The interface between the ADC16DV160 and a receiver block can be easily verified and optimized via fixed pattern generation and output clock position features. The digital data is provided via dual data rate LVDS outputs – making possible the 68-pin, 10 mm x 10 mm VQFN package. The ADC16DV160 operates on dual power supplies of +1.8V and +3.0V with a power-down feature to reduce power consumption to very low levels while allowing fast recovery to full operation.
The ADC16DV160 is a monolithic dual channel high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 160 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16DV160 can be re-calibrated at any time through the 3-wire Serial Peripheral Interface (SPI). An integrated low noise and stable voltage reference and differential reference buffer amplifier eases board level design. The on-chip duty cycle stabilizer with low additive jitter allows a wide range of input clock duty cycles without compromising dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The interface between the ADC16DV160 and a receiver block can be easily verified and optimized via fixed pattern generation and output clock position features. The digital data is provided via dual data rate LVDS outputs – making possible the 68-pin, 10 mm x 10 mm VQFN package. The ADC16DV160 operates on dual power supplies of +1.8V and +3.0V with a power-down feature to reduce power consumption to very low levels while allowing fast recovery to full operation.
