AM2432 Series
Dual-core Arm® Cortex®-R5F-based MCU with industrial communications and security up to 800 MHz
Manufacturer: Texas Instruments
Catalog
Dual-core Arm® Cortex®-R5F-based MCU with industrial communications and security up to 800 MHz
Key Features
• Up to 2× Dual-core Arm Cortex-R5F MCU subsystems operating at up to 800MHz, highly-integrated for real-time processingDual-core Arm Cortex-R5F clusters support dual-core and single-core operation32KB I-cache and 32KB D-cache per R5F core with SECDED ECC on all memoriesSingle-core: 128KB TCM per cluster (128KB TCM per R5F core)Dual-core: 128KB TCM per cluster (64KB TCM per R5F core)1× Single-core Arm Cortex-M4F MCU at up to 400MHz256KB SRAM with SECDED ECCUp to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banksEach memory bank can be allocated to a single core to facilitate software task partitioningDDR Subsystem (DDRSS)Supports LPDDR4, DDR4 memory types16-bit data bus with inline ECCSupports speeds up to 1600 MT/sDevice Management Security Controller (DMSC-L)Centralized SoC system controllerManages system services including initial boot, security, and clock/reset/power managementCommunication with various processing units over message managerSimplified interface for optimizing unused peripheralsOn-Chip Debug functionality through JTAG and Trace interfaces)Data Movement Subsystem (DMSS)Block Copy DMA (BCDMA)Packet DMA (PKTDMA)Secure Proxy (SEC_PROXY)Ring Accelerator (RINGACC)Time Sync SubsystemCentral Platform Time Sync (CPTS) moduleTimer Manager (TIMERMANAGER) with 1024 timersTime Sync and Compare event interrupt routers2× Gigabit Industrial Communication Subsystems (PRU_ICSSG)Optional support for Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and other Networking ProtocolsBackwards compatibility with 10/100Mb PRU-ICSSEach PRU_ICSSG contains:3× PRU RISC Cores per Slice (2× Slice per PRU_ICSSG)PRU General Use core (PRU)PRU Real-Time Unit core (PRU-RTU)PRU Transmit core (PRU-TX)Each PRU core supports the following features:Instruction RAM with ECCBroadside RAMMultiplier with optional accumulator (MAC)CRC16/32 hardware acceleratorByte swap for Big/Little Endian conversionSUM32 hardware accelerator for UDP checksumTask Manager for preemption supportUp to 2× Ethernet portsRGMII (10/100/1000)MII (10/100)Three Data RAMs with ECC8 banks of 30 × 32-bit register scratchpad memoryInterrupt controller and task manager2× 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions18× Sigma-Delta Filter Module (SDFM) interfacesShort circuit logicOver-current logic6× Multi-protocol position encoder interfaces1× Enhanced Capture Module (ECAP)16550-compatible UARTDedicated 192MHz clock to support 12Mbps PROFIBUSSecure boot supportedHardware-enforced Root-of-Trust (RoT)Support to switch RoT via backup keySupport for takeover protection, IP protection, and anti-roll back protectionCryptographic acceleration supportedSession-aware cryptographic engine with ability to auto-switch key-material based on incoming data streamSupports cryptographic coresAES – 128-/192-/256-Bit key sizes3DES – 56-/112-/168-Bit key sizesMD5, SHA1SHA2 – 224-/256-/384-/512-Bit key sizesDRBG with true random number generatorPKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure bootDMA supportDebugging securityExtensive firewall support for isolationSecure watchdog/timer/IPCSecure storage supportOn-the-Fly encryption support for OSPI interface in XIP modeNetworking security support for data (Payload) encryption/authentication via packet based hardware cryptographic engineSecurity co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security6× Inter-Integrated Circuit (I2C) ports9× Universal Asynchronous Receive/Transmit (UART) modules1× 12-bit Analog-to-Digital Converters (ADC)Configurable sample rate up to 4MSPS8× multiplexed analog inputs7× Multichannel Serial Peripheral Interfaces (SPI) controllers3× General-Purpose I/O (GPIO) modules9× Enhanced Pulse-Width Modulator (EPWM) modules3× Enhanced Capture (ECAP) modules3× Enhanced Quadrature Encoder Pulse (EQEP) modules2× Modular Controller Area Network (MCAN) modules with full CAN-FD support2× Fast Serial Interface Transmitter (FSITX) cores6× Fast Serial Interface Receiver (FSIRX) coresHigh-speed interfaces:1× Integrated Ethernet switch supporting: (CPSW)Up to 2 external Ethernet portsRGMII (10/100/1000)RMII (10/100)IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTPClause 45 MDIO PHY managementEnergy efficient Ethernet (802.3az)1× PCI-Express Gen2 controller (PCIE)Supports Gen2 Single Lane operation1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)Port configurable as USB Host, USB Device, or USB Dual-Role deviceUSB Device: High-speed (480Mbps) and Full-speed (12Mbps)USB Host: SuperSpeed Gen1 (5Gbps), High-speed (480Mbps), Full-speed (12Mbps), and Low-speed (1.5Mbps)Integrated USB VBUS detection1× Serializer/Deserializer (SERDES)One SERDES PHY lane to support eitherPCI-Express Gen2 or USB SuperSpeed Gen12× Multimedia Card/Secure Digital (MMCSD) interfacesOne 8-bit for eMMC (MMCSD0)One 4-bit for MMCSD/SDIO (MMCSD1)Integrated analog switch for voltage switching from 3.3V to 1.8V for high-speed cards1× General-Purpose Memory Controller (GPMC)16-bit parallel bus with 133MHz clock or32-bit parallel bus with 100MHz clockError Location Module (ELM) support1× Flash Subsystem (FSS) for external memory configurable as either:1× Octal SPI (OSPI) flash interfaceor 1× Quad SPI (QSPI) flash interfaceSimplified power sequencing requirementsDual-voltage I/O Support (3.3V / 1.8V)Integrated SDIO LDO for handling automatic voltage transition for SD interfaceIntegrated voltage supervisor for monitoring over-voltage and under-voltage conditionsIntegrated power supply glitch detector for detecting fast supply transientsFunctional safety:Functional Safety-CompliantDeveloped for functional safety applicationsDocumentation available to aid IEC 61508 functional safety system designSystematic capability up to SIL 3Hardware integrity up to SIL 2Safety-related certificationIEC 61508 certification by TUV SUDECC or parity on calculation-critical memoriesBuilt-In Self-Test (BIST) for CPU and on-chip RAMError Signaling Module (ESM) with dedicated error pinECC and parity on select internal bus interconnectsRun-time safety diagnostics, including:Voltage, Temperature, and Clock MonitoringWindowed Watchdog TimersCRC Engine for memory integrity checksMCU domain with dedicated memory, interfaces, and M4FSS capable of isolation from the larger SoC with Freedom From Interference (FFI) features:Separate interconnectFirewalls and timeout gasketsControlled reset isolationDedicated MCU PLL and MMR controlSeparate I/O voltage supply railSupports boot from OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, UART, I2C, MMCSD, eMMC, USB, PCIe, and Ethernet interfaces.16-nm FinFET technologyALV: 17.2mm × 17.2mm, 0.8mm pitch(441-pin) [Lidded] Flip-Chip Ball Grid Array(FCBGA)ALX: 11.0mm × 11.0mm, 0.5mm pitch(293-pin) [Overmolded] Flip-Chip Chip Scale Package(FCCSP)Up to 2× Dual-core Arm Cortex-R5F MCU subsystems operating at up to 800MHz, highly-integrated for real-time processingDual-core Arm Cortex-R5F clusters support dual-core and single-core operation32KB I-cache and 32KB D-cache per R5F core with SECDED ECC on all memoriesSingle-core: 128KB TCM per cluster (128KB TCM per R5F core)Dual-core: 128KB TCM per cluster (64KB TCM per R5F core)1× Single-core Arm Cortex-M4F MCU at up to 400MHz256KB SRAM with SECDED ECCUp to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banksEach memory bank can be allocated to a single core to facilitate software task partitioningDDR Subsystem (DDRSS)Supports LPDDR4, DDR4 memory types16-bit data bus with inline ECCSupports speeds up to 1600 MT/sDevice Management Security Controller (DMSC-L)Centralized SoC system controllerManages system services including initial boot, security, and clock/reset/power managementCommunication with various processing units over message managerSimplified interface for optimizing unused peripheralsOn-Chip Debug functionality through JTAG and Trace interfaces)Data Movement Subsystem (DMSS)Block Copy DMA (BCDMA)Packet DMA (PKTDMA)Secure Proxy (SEC_PROXY)Ring Accelerator (RINGACC)Time Sync SubsystemCentral Platform Time Sync (CPTS) moduleTimer Manager (TIMERMANAGER) with 1024 timersTime Sync and Compare event interrupt routers2× Gigabit Industrial Communication Subsystems (PRU_ICSSG)Optional support for Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and other Networking ProtocolsBackwards compatibility with 10/100Mb PRU-ICSSEach PRU_ICSSG contains:3× PRU RISC Cores per Slice (2× Slice per PRU_ICSSG)PRU General Use core (PRU)PRU Real-Time Unit core (PRU-RTU)PRU Transmit core (PRU-TX)Each PRU core supports the following features:Instruction RAM with ECCBroadside RAMMultiplier with optional accumulator (MAC)CRC16/32 hardware acceleratorByte swap for Big/Little Endian conversionSUM32 hardware accelerator for UDP checksumTask Manager for preemption supportUp to 2× Ethernet portsRGMII (10/100/1000)MII (10/100)Three Data RAMs with ECC8 banks of 30 × 32-bit register scratchpad memoryInterrupt controller and task manager2× 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions18× Sigma-Delta Filter Module (SDFM) interfacesShort circuit logicOver-current logic6× Multi-protocol position encoder interfaces1× Enhanced Capture Module (ECAP)16550-compatible UARTDedicated 192MHz clock to support 12Mbps PROFIBUSSecure boot supportedHardware-enforced Root-of-Trust (RoT)Support to switch RoT via backup keySupport for takeover protection, IP protection, and anti-roll back protectionCryptographic acceleration supportedSession-aware cryptographic engine with ability to auto-switch key-material based on incoming data streamSupports cryptographic coresAES – 128-/192-/256-Bit key sizes3DES – 56-/112-/168-Bit key sizesMD5, SHA1SHA2 – 224-/256-/384-/512-Bit key sizesDRBG with true random number generatorPKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure bootDMA supportDebugging securityExtensive firewall support for isolationSecure watchdog/timer/IPCSecure storage supportOn-the-Fly encryption support for OSPI interface in XIP modeNetworking security support for data (Payload) encryption/authentication via packet based hardware cryptographic engineSecurity co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security6× Inter-Integrated Circuit (I2C) ports9× Universal Asynchronous Receive/Transmit (UART) modules1× 12-bit Analog-to-Digital Converters (ADC)Configurable sample rate up to 4MSPS8× multiplexed analog inputs7× Multichannel Serial Peripheral Interfaces (SPI) controllers3× General-Purpose I/O (GPIO) modules9× Enhanced Pulse-Width Modulator (EPWM) modules3× Enhanced Capture (ECAP) modules3× Enhanced Quadrature Encoder Pulse (EQEP) modules2× Modular Controller Area Network (MCAN) modules with full CAN-FD support2× Fast Serial Interface Transmitter (FSITX) cores6× Fast Serial Interface Receiver (FSIRX) coresHigh-speed interfaces:1× Integrated Ethernet switch supporting: (CPSW)Up to 2 external Ethernet portsRGMII (10/100/1000)RMII (10/100)IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTPClause 45 MDIO PHY managementEnergy efficient Ethernet (802.3az)1× PCI-Express Gen2 controller (PCIE)Supports Gen2 Single Lane operation1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)Port configurable as USB Host, USB Device, or USB Dual-Role deviceUSB Device: High-speed (480Mbps) and Full-speed (12Mbps)USB Host: SuperSpeed Gen1 (5Gbps), High-speed (480Mbps), Full-speed (12Mbps), and Low-speed (1.5Mbps)Integrated USB VBUS detection1× Serializer/Deserializer (SERDES)One SERDES PHY lane to support eitherPCI-Express Gen2 or USB SuperSpeed Gen12× Multimedia Card/Secure Digital (MMCSD) interfacesOne 8-bit for eMMC (MMCSD0)One 4-bit for MMCSD/SDIO (MMCSD1)Integrated analog switch for voltage switching from 3.3V to 1.8V for high-speed cards1× General-Purpose Memory Controller (GPMC)16-bit parallel bus with 133MHz clock or32-bit parallel bus with 100MHz clockError Location Module (ELM) support1× Flash Subsystem (FSS) for external memory configurable as either:1× Octal SPI (OSPI) flash interfaceor 1× Quad SPI (QSPI) flash interfaceSimplified power sequencing requirementsDual-voltage I/O Support (3.3V / 1.8V)Integrated SDIO LDO for handling automatic voltage transition for SD interfaceIntegrated voltage supervisor for monitoring over-voltage and under-voltage conditionsIntegrated power supply glitch detector for detecting fast supply transientsFunctional safety:Functional Safety-CompliantDeveloped for functional safety applicationsDocumentation available to aid IEC 61508 functional safety system designSystematic capability up to SIL 3Hardware integrity up to SIL 2Safety-related certificationIEC 61508 certification by TUV SUDECC or parity on calculation-critical memoriesBuilt-In Self-Test (BIST) for CPU and on-chip RAMError Signaling Module (ESM) with dedicated error pinECC and parity on select internal bus interconnectsRun-time safety diagnostics, including:Voltage, Temperature, and Clock MonitoringWindowed Watchdog TimersCRC Engine for memory integrity checksMCU domain with dedicated memory, interfaces, and M4FSS capable of isolation from the larger SoC with Freedom From Interference (FFI) features:Separate interconnectFirewalls and timeout gasketsControlled reset isolationDedicated MCU PLL and MMR controlSeparate I/O voltage supply railSupports boot from OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, UART, I2C, MMCSD, eMMC, USB, PCIe, and Ethernet interfaces.16-nm FinFET technologyALV: 17.2mm × 17.2mm, 0.8mm pitch(441-pin) [Lidded] Flip-Chip Ball Grid Array(FCBGA)ALX: 11.0mm × 11.0mm, 0.5mm pitch(293-pin) [Overmolded] Flip-Chip Chip Scale Package(FCCSP)
Description
AI
AM243x is an extension of Sitara’s industrial-grade portfolio into high-performance microcontrollers. The AM243x device is built for industrial applications, such as motor drives and remote I/O modules, which require a combination of real-time communications and processing. The AM243x family provides scalable performance with up to four Cortex-R5F MCUs, one Cortex-M4F, and two instances of Sitara’s gigabit TSN-enabled PRU_ICSSG.
The AM243x SoC architecture was designed to provide best-in-class real-time performance through the high-performance Arm Cortex-R5F cores, Tightly-Coupled Memory (TCM) banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM243x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, ECAPs, PWMs, and encoder interfaces help enable a number of different architectures found in these systems.
The SoC provides flexible industrial communications capability including full protocol stacks for EtherCAT target, PROFINET device, EtherNet/IP adapter, and IO-Link Controller. The PRU_ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU_ICSSG enables additional interfaces including a UART interface, sigma delta decimation filters, and absolute encoder interfaces.
Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM243x also supports secure boot.
AM243x is an extension of Sitara’s industrial-grade portfolio into high-performance microcontrollers. The AM243x device is built for industrial applications, such as motor drives and remote I/O modules, which require a combination of real-time communications and processing. The AM243x family provides scalable performance with up to four Cortex-R5F MCUs, one Cortex-M4F, and two instances of Sitara’s gigabit TSN-enabled PRU_ICSSG.
The AM243x SoC architecture was designed to provide best-in-class real-time performance through the high-performance Arm Cortex-R5F cores, Tightly-Coupled Memory (TCM) banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM243x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, ECAPs, PWMs, and encoder interfaces help enable a number of different architectures found in these systems.
The SoC provides flexible industrial communications capability including full protocol stacks for EtherCAT target, PROFINET device, EtherNet/IP adapter, and IO-Link Controller. The PRU_ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU_ICSSG enables additional interfaces including a UART interface, sigma delta decimation filters, and absolute encoder interfaces.
Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM243x also supports secure boot.
