CS5332 Series

Two-Phase Buck Controller with Integrated Gate Drivers for VRM 9.0

Catalog

Two-Phase Buck Controller with Integrated Gate Drivers for VRM 9.0

Part	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Topology	Number of Outputs	Output Type	Voltage - Supply (Vcc/Vdd) [Max]	Voltage - Supply (Vcc/Vdd) [Min]	Function	Control Features	Output Configuration	Output Phases	Clock Sync	Frequency - Switching [Min]	Frequency - Switching [Max]	Package / Case	Package / Case [x]	Package / Case [y]	Supplier Device Package	Synchronous Rectifier
ON Semiconductor CS5332GDW28	Surface Mount	70 °C	0 °C	Buck	2	Transistor Driver	16 V	4.2 V	Step-Down	Current Limit Power Good Soft Start	Positive	2		200 kHz	800 kHz	28-SOIC	0.295 in	7.5 mm	28-SOIC
ON Semiconductor CS5332GDWR28	Surface Mount	70 °C	0 °C	Buck	2	Transistor Driver	16 V	4.2 V	Step-Down	Current Limit Power Good Soft Start	Positive	2		200 kHz	800 kHz	28-SOIC	0.295 in	7.5 mm	28-SOIC

Catalog

Two-Phase Buck Controller with Integrated Gate Drivers for VRM 9.0

Key Features

• Enhanced V2Control Method

• VRM 9.0 Compatible 5-Bit DAC with 1.0% Accuracy

• Adjustable Output Voltage Positioning

• 4 On-Board GATE Drivers

• 200 kHz to 800 kHz Operation Set by Resistor

• Current Sensed through Buck Inductors, or Sense Resistors

• Hiccup Mode Current Limit

• Individual Current Limits for Each Phase

• On-Board Current Sense Amplifiers

• 3.3 V, 1.0 mA Reference Output

• 5.0 V and/or 12 V Operation

• On/Off Control (through Soft Start Pin)

• Power Good Output with Internal Delay

Description

The CS5332 is a two-phase step down controller which incorporates all control functions required to power high performance processors and high current power supplies. Proprietary multi-phase architecture guarantees balanced load current distribution and reduces overall solution cost in high current applications. Enhanced V2™control architecture provides the fastest possible transient response, excellent overall regulation, and ease of use.The CS5332 multi-phase architecture reduces output voltage and input current ripple, allowing for a significant reduction in inductor values and a corresponding increase in inductor current slew rate. This approach allows a considerable reduction in input and output capacitor requirements, as well as reducing overall solution size and cost.