LMK04610 Series
Ultra low-noise and low power JESD204B compliant clock jitter cleaner with dual PLLs
Manufacturer: Texas Instruments
Catalog
Ultra low-noise and low power JESD204B compliant clock jitter cleaner with dual PLLs
Key Features
• Dual-loop PLL architectureUltra low noise (10 kHz to 20 MHz):48-fs RMS jitter at 1966.08 MHz50-fs RMS jitter at 983.04 MHz61-fs RMS jitter at 122.88 MHz–165-dBc/Hz noise floor at 122.88 MHzJESD204B supportSingle shot, pulsed, and continuous SYSREF10 differential output clocks in 8 frequency groupsProgrammable output swing between 700 mVpp to 1600 mVppEach output pair can be configured to SYSREF clock output16-bit channel dividerMinimum SYSREF frequency of 25 kHzMaximum output frequency of 2 GHzPrecision digital delay, dynamically adjustableDigital delay (DDLY) of ½ × clock distribution path frequency (2 GHz maximum)60-ps step analog delay50% duty cycle output divides, 1 to 65535(even and odd)Two reference inputsHoldover mode, when inputs are lostAutomatic and manual switch-over modesLoss-of-signal (LOS) detection0.88-W typical power consumption with 10 outputs activeOperates typically from a 1.8-V (outputs, inputs) and 3.3-V supply (digital, PLL1, PLL2_OSC, PLL2 core)Fully integrated programmable loop filterPLL2PLL2 phase detector rate up to 250 MHzOSCin frequency-doublerIntegrated low-noise VCOInternal power conditioning: better than –80 dBc PSRR on VDDO for 122.88-MHz differential outputs3- or 4-wire SPI interface (4-wire is default)–40ºC to +85ºC industrial ambient temperatureSupports 105ºC PCB temperature (measured at thermal pad)LMK04610: 8-mm × 8-mm VQFN-56 package with 0.5-mm pitchDual-loop PLL architectureUltra low noise (10 kHz to 20 MHz):48-fs RMS jitter at 1966.08 MHz50-fs RMS jitter at 983.04 MHz61-fs RMS jitter at 122.88 MHz–165-dBc/Hz noise floor at 122.88 MHzJESD204B supportSingle shot, pulsed, and continuous SYSREF10 differential output clocks in 8 frequency groupsProgrammable output swing between 700 mVpp to 1600 mVppEach output pair can be configured to SYSREF clock output16-bit channel dividerMinimum SYSREF frequency of 25 kHzMaximum output frequency of 2 GHzPrecision digital delay, dynamically adjustableDigital delay (DDLY) of ½ × clock distribution path frequency (2 GHz maximum)60-ps step analog delay50% duty cycle output divides, 1 to 65535(even and odd)Two reference inputsHoldover mode, when inputs are lostAutomatic and manual switch-over modesLoss-of-signal (LOS) detection0.88-W typical power consumption with 10 outputs activeOperates typically from a 1.8-V (outputs, inputs) and 3.3-V supply (digital, PLL1, PLL2_OSC, PLL2 core)Fully integrated programmable loop filterPLL2PLL2 phase detector rate up to 250 MHzOSCin frequency-doublerIntegrated low-noise VCOInternal power conditioning: better than –80 dBc PSRR on VDDO for 122.88-MHz differential outputs3- or 4-wire SPI interface (4-wire is default)–40ºC to +85ºC industrial ambient temperatureSupports 105ºC PCB temperature (measured at thermal pad)LMK04610: 8-mm × 8-mm VQFN-56 package with 0.5-mm pitch
Description
AI
The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support.
The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support.
