SN74AVC2T45-Q1 Series

Automotive Dual-Bit Dual-Supply Bus Transceiver with Config Voltage Translation and 3-State

Catalog

Automotive Dual-Bit Dual-Supply Bus Transceiver with Config Voltage Translation and 3-State

Part	Number of Circuits	Qualification	Output Type	Voltage - VCCA [Min]	Voltage - VCCA [Max]	Channels per Circuit	Data Rate	Mounting Type	Grade	Channel Type	Voltage - VCCB [Max]	Voltage - VCCB [Min]	Package / Case [y]	Package / Case	Package / Case [y]	Operating Temperature [Max]	Operating Temperature [Min]	Translator Type
Texas Instruments CAVC2T45TDCURQ1	1	AEC-Q100	Non-Inverted Tri-State	1.2 V	3.6 V	2	500 Mbps	Surface Mount	Automotive	Bidirectional	3.6 V	1.2 V	2.3 mm	8-VFSOP	0.091 in	105 °C	-40 °C	Voltage Level

Catalog

Automotive Dual-Bit Dual-Supply Bus Transceiver with Config Voltage Translation and 3-State

Key Features

• Qualified for automotive applicationsControl inputs VIH/VIL levels are referenced to VCCA voltageFully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply rangeOperating temperature from -40°C to 105°CI/Os are 4.6V tolerantIoff supports partial-power-down mode operationMaximum data rates500Mbps (1.8V to 3.3V translation)320Mbps (< 1.8V to 3.3V translation)320Mbps (translate to 2.5V or 1.8V)280Mbps (translate to 1.5V)240Mbps (translate to 1.2V)Latch-up performance exceeds 100mA per JESD 78, Class IIESD protection exceeds JESD 228000V human-body model (A114-A)200V machine model (A115-A)1000V charged-device model (C101)Qualified for automotive applicationsControl inputs VIH/VIL levels are referenced to VCCA voltageFully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply rangeOperating temperature from -40°C to 105°CI/Os are 4.6V tolerantIoff supports partial-power-down mode operationMaximum data rates500Mbps (1.8V to 3.3V translation)320Mbps (< 1.8V to 3.3V translation)320Mbps (translate to 2.5V or 1.8V)280Mbps (translate to 1.5V)240Mbps (translate to 1.2V)Latch-up performance exceeds 100mA per JESD 78, Class IIESD protection exceeds JESD 228000V human-body model (A114-A)200V machine model (A115-A)1000V charged-device model (C101)

Description

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes. The SN74AVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. The SN74AVC2T45 is designed so that the DIR input is powered by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when powered down. The VCC isolation feature makes sure that if either VCC input is at GND, both ports are in the high-impedance state. This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes. The SN74AVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. The SN74AVC2T45 is designed so that the DIR input is powered by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when powered down. The VCC isolation feature makes sure that if either VCC input is at GND, both ports are in the high-impedance state.