74LV08D-Q100 Series

Quad 2-input AND gate

Manufacturer: Freescale Semiconductor - NXP

Catalog

Quad 2-input AND gate

Part	Operating Temperature [Max]	Operating Temperature [Min]	Input Logic Level - Low [Max]	Input Logic Level - Low [Min]	Package / Case	Package / Case	Package / Case	Number of Circuits	Input Logic Level - High [Min] [custom]	Input Logic Level - High [Max] [custom]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Mounting Type	Supplier Device Package	Current - Quiescent (Max) [Max]	Logic Type	Number of Inputs	Max Propagation Delay @ V, Max CL	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case [custom]	Package / Case [custom]	Package / Case [x]	Package / Case [y]	Qualification	Grade
Freescale Semiconductor - NXP 74LV08DB,112	125 °C	-40 °C	0.8 V	0.3 V	5.3 mm	14-SSOP	0.209 "	4	0.9 V	2 V	12 mA	12 mA	Surface Mount	14-SSOP	40 µA	AND Gate	2	9 ns	1 V	5.5 V
Freescale Semiconductor - NXP 74LV08PW,118	125 °C	-40 °C	0.8 V	0.3 V		14-TSSOP		4	0.9 V	2 V	12 mA	12 mA	Surface Mount	14-TSSOP	40 µA	AND Gate	2	9 ns	1 V	5.5 V	0.173 "	4.4 mm
Freescale Semiconductor - NXP 74LV08D-Q100,118	125 °C	-40 °C	0.8 V	0.3 V		14-SOIC		4	0.9 V	2 V	12 mA	12 mA	Surface Mount	14-SO	40 µA	AND Gate	2	9 ns	1 V	5.5 V			0.154 in	3.9 mm	AEC-Q100	Automotive
Freescale Semiconductor - NXP 74LV08PW,112	125 °C	-40 °C	0.8 V	0.3 V		14-TSSOP		4	0.9 V	2 V	12 mA	12 mA	Surface Mount	14-TSSOP	40 µA	AND Gate	2	9 ns	1 V	5.5 V	0.173 "	4.4 mm
Freescale Semiconductor - NXP 74LV08PW-Q100,118	125 °C	-40 °C	0.8 V	0.3 V		14-TSSOP		4	0.9 V	2 V	12 mA	12 mA	Surface Mount	14-TSSOP	40 µA	AND Gate	2	9 ns	1 V	5.5 V	0.173 "	4.4 mm			AEC-Q100	Automotive
Freescale Semiconductor - NXP 74LV08D,112	125 °C	-40 °C	0.8 V	0.3 V		14-SOIC		4	0.9 V	2 V	12 mA	12 mA	Surface Mount	14-SO	40 µA	AND Gate	2	9 ns	1 V	5.5 V			0.154 in	3.9 mm

Catalog

Quad 2-input AND gate

Key Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• Wide supply voltage range from 1.0 V to 5.5 V

• CMOS low power dissipation

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Optimized for low voltage applications: 1.0 V to 3.6 V

• Accepts TTL input levels between VCC= 2.7 V and VCC= 3.6 V

• Typical output ground bounce < 0.8 V at VCC= 3.3 V and Tamb= 25 °C

• Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC= 3.3 V and Tamb= 25 °C

• Complies with JEDEC standards:

• ESD protection:

• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

Description

The 74LV08-Q100 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.