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AMIC120

AMIC120 Series

Sitara processor; Arm Cortex-A9; 10+ Ethernet protocols, encoder protocols

Manufacturer: Texas Instruments

Catalog

Sitara processor; Arm Cortex-A9; 10+ Ethernet protocols, encoder protocols

Key Features

• HighlightsSitara™ ARM®Cortex®-A9 32-Bit RISC Processor With Processing Speed up to 300 MHzNEON™ SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor32KB of Both L1 Instruction and Data Cache256KB of L2 Cache or L3 RAM32-Bit LPDDR2, DDR3, and DDR3L SupportGeneral-Purpose Memory Support (NAND, NOR, SRAM) Supporting up to 16-Bit ECCReal-Time Clock (RTC)Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY10, 100, and 1000 Ethernet Switch Supporting up to Two Ports (Only 1 Port is Pinned out on this Device)Serial Interfaces:Six UARTs, Two McASPs, Five McSPIs, Three I2C Ports, One QSPI, and One HDQ or 1-WireSecurityCrypto Hardware Accelerators (AES, SHA, RNG, DES, and 3DES)Two 12-Bit Successive Approximation Register (SAR) ADCsUp to Three 32-Bit Enhanced Capture (eCAP) ModulesUp to Three Enhanced Quadrature Encoder Pulse (eQEP) ModulesUp to Six Enhanced High-Resolution PWM (eHRPWM) ModulesMPU SubsystemARM Cortex-A9 32-Bit RISC Microprocessor With Processing Speed up to 300 MHz32KB of Both L1 Instruction and Data Cache256KB of L2 Cache (Option to Configure as L3 RAM)256KB of On-Chip Boot ROM64KB of On-Chip RAMEmulation and DebugJTAGEmbedded Trace BufferInterrupt ControllerOn-Chip Memory (Shared L3 RAM)256KB of General-Purpose On-Chip Memory Controller (OCMC) RAMAccessible to All MastersSupports Retention for Fast WakeupUp to 512KB of Total Internal RAM(256KB of ARM Memory Configured as L3 RAM + 256KB of OCMC RAM)External Memory Interfaces (EMIFs)DDR Controllers:LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate)DDR3 and DDR3L: 400-MHz Clock (DDR-800 Data Rate)32-Bit Data Bus2GB of Total Addressable SpaceSupports One x32, Two x16, or Four x8 Memory Device ConfigurationsGeneral-Purpose Memory Controller (GPMC)Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, and SRAM)Uses BCH Code to Support 4-, 8-, or 16-Bit ECCUses Hamming Code to Support 1-Bit ECCError Locator Module (ELM)Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH AlgorithmSupports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH AlgorithmsProgrammable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)Supports Protocols such as EtherCAT®, PROFIBUS®, PROFINET®, and EtherNet/IP™, EnDat 2.2, and MoreTwo Programmable Real-Time Units (PRUs) Subsystems With Two PRU Cores EachEach Core is a 32-Bit Load and Store RISC Processor Capable of Running at 200 MHz12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Instruction RAM With Single-Error Detection (Parity)8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Data RAM With Single-Error Detection (Parity)Single-Cycle 32-Bit Multiplier With 64-Bit AccumulatorEnhanced GPIO Module Provides Shift-In and Shift-Out Support and Parallel Latch on External Signal12KB (PRU-ICSS1 Only) of Shared RAM With Single-Error Detection (Parity)Three 120-Byte Register Banks Accessible by Each PRUInterrupt Controller Module (INTC) for Handling System Input EventsLocal Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSSPeripherals Inside the PRU-ICSSOne UART Port With Flow Control Pins, Supports up to 12 MbpsOne eCAP ModuleTwo MII Ethernet Ports that Support Industrial Ethernet, such as EtherCATOne MDIO PortIndustrial Communication is Supported by Two PRU-ICSS SubsystemsPower, Reset, and Clock Management (PRCM) ModuleControls the Entry and Exit of Deep-Sleep ModesResponsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On SequencingClocksIntegrated High-Frequency Oscillator Used to Generate a Reference Clock (19.2, 24, 25, and 26 MHz) for Various System and Peripheral ClocksSupports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power ConsumptionFive ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB, and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, and Ethernet)PowerTwo Nonswitchable Power Domains (RTC and Wake-Up Logic [WAKE-UP])Two Switchable Power Domains (MPU Subsystem, Peripherals and Infrastructure [PER])Dynamic Voltage Frequency Scaling (DVFS)Real-Time Clock (RTC)Real-Time Date (Day, Month, Year, and Day of Week) and Time (Hours, Minutes, and Seconds) InformationInternal 32.768-kHz Oscillator, RTC Logic, and 1.1-V Internal LDOIndependent Power-On-Reset (RTC_PWRONRSTn) InputDedicated Input Pin (RTC_WAKEUP) for External Wake EventsProgrammable Alarm Can Generate Internal Interrupts to the PRCM for Wakeup or Cortex-A9 for Event NotificationProgrammable Alarm Can Be Used With External Output (RTC_PMIC_EN) to Enable the Power-Management IC to Restore Non-RTC Power DomainsPeripheralsUp to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHYUp to Two Industrial Gigabit Ethernet MACs(10, 100, and 1000 Mbps)Integrated SwitchMAC Supports MII, RMII, and RGMII and MDIO InterfacesEthernet MAC and Switch Can Operate Independent of Other FunctionsIEEE 1588v2 Precision Time Protocol (PTP)Up to Two CAN PortsSupports CAN Version 2 Parts A and BUp to Two Multichannel Audio Serial Ports (McASPs)Transmit and Receive Clocks up to 50 MHzUp to Four Serial Data Pins Per McASP Port With Independent TX and RX ClocksSupports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar FormatsSupports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)FIFO Buffers for Transmit and Receive (256 Bytes)Up to Six UARTsAll UARTs Support IrDA and CIR ModesAll UARTs Support RTS and CTS Flow ControlUART1 Supports Full Modem ControlUp to Five Master and Slave McSPIsMcSPI0–McSPI2 Support up to Four Chip SelectsMcSPI3 and McSPI4 Support up to Two Chip SelectsUp to 48 MHzOne Quad-SPISupports eXecute In Place (XIP) from Serial NOR FLASHOne Dallas 1-Wire®and HDQ Serial InterfaceUp to Three MMC, SD, and SDIO Ports1-, 4-, and 8-Bit MMC, SD, and SDIO Modes1.8- or 3.3-V Operation on All PortsUp to 48-MHz ClockSupports Card Detect and Write ProtectComplies With MMC4.3 and SD and SDIO 2.0 SpecificationsUp to Three I2C Master and Slave InterfacesStandard Mode (up to 100 kHz)Fast Mode (up to 400 kHz)Up to Six Banks of General-Purpose I/O (GPIO)32 GPIOs per Bank (Multiplexed With Other Functional Pins)GPIOs Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)Up to Three External DMA Event Inputs That Can Also be Used as Interrupt InputsTwelve 32-Bit General-Purpose TimersDMTIMER1 is a 1-ms Timer Used for Operating System (OS) TicksDMTIMER4–DMTIMER7 are Pinned OutOne Public Watchdog TimerOne Free-Running, High-Resolution 32-kHz Counter (synctimer32K)Two 12-Bit SAR ADCs (ADC0, ADC1)867K Samples Per SecondInput Can Be Selected from Any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog SwitchUp to Three 32-Bit eCAP ModulesConfigurable as Three Capture Inputs or Three Auxiliary PWM OutputsUp to Six Enhanced eHRPWM ModulesDedicated 16-Bit Time-Base Counter With Time and Frequency ControlsConfigurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric OutputsUp to Three 32-Bit eQEP ModulesDevice IdentificationFactory Programmable Electrical Fuse Farm (FuseFarm)Production IDDevice Part Number (Unique JTAG ID)Device Revision (Readable by Host ARM)Debug Interface SupportJTAG and cJTAG for ARM (Cortex-A9 and PRCM) and PRU-ICSS DebugSupports Real-Time Trace Pins (for Cortex-A9)64-KB Embedded Trace Buffer (ETB)Supports Device Boundary ScanSupports IEEE 1500DMAOn-Chip Enhanced DMA Controller (EDMA) Has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA ChannelsEDMA is Used for:Transfers to and from On-Chip MemoriesTransfers to and from External Storage (EMIF, GPMC, and Slave Peripherals)InterProcessor Communication (IPC)Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between the Cortex-A9, PRCM, and PRU-ICSSBoot ModesBoot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input PinPackage491-Pin BGA Package (17-mm × 17-mm) (ZDN Suffix), 0.65-mm Ball Pitch With Via Channel Array Technology to Enable Low-Cost RoutingHighlightsSitara™ ARM®Cortex®-A9 32-Bit RISC Processor With Processing Speed up to 300 MHzNEON™ SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor32KB of Both L1 Instruction and Data Cache256KB of L2 Cache or L3 RAM32-Bit LPDDR2, DDR3, and DDR3L SupportGeneral-Purpose Memory Support (NAND, NOR, SRAM) Supporting up to 16-Bit ECCReal-Time Clock (RTC)Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY10, 100, and 1000 Ethernet Switch Supporting up to Two Ports (Only 1 Port is Pinned out on this Device)Serial Interfaces:Six UARTs, Two McASPs, Five McSPIs, Three I2C Ports, One QSPI, and One HDQ or 1-WireSecurityCrypto Hardware Accelerators (AES, SHA, RNG, DES, and 3DES)Two 12-Bit Successive Approximation Register (SAR) ADCsUp to Three 32-Bit Enhanced Capture (eCAP) ModulesUp to Three Enhanced Quadrature Encoder Pulse (eQEP) ModulesUp to Six Enhanced High-Resolution PWM (eHRPWM) ModulesMPU SubsystemARM Cortex-A9 32-Bit RISC Microprocessor With Processing Speed up to 300 MHz32KB of Both L1 Instruction and Data Cache256KB of L2 Cache (Option to Configure as L3 RAM)256KB of On-Chip Boot ROM64KB of On-Chip RAMEmulation and DebugJTAGEmbedded Trace BufferInterrupt ControllerOn-Chip Memory (Shared L3 RAM)256KB of General-Purpose On-Chip Memory Controller (OCMC) RAMAccessible to All MastersSupports Retention for Fast WakeupUp to 512KB of Total Internal RAM(256KB of ARM Memory Configured as L3 RAM + 256KB of OCMC RAM)External Memory Interfaces (EMIFs)DDR Controllers:LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate)DDR3 and DDR3L: 400-MHz Clock (DDR-800 Data Rate)32-Bit Data Bus2GB of Total Addressable SpaceSupports One x32, Two x16, or Four x8 Memory Device ConfigurationsGeneral-Purpose Memory Controller (GPMC)Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, and SRAM)Uses BCH Code to Support 4-, 8-, or 16-Bit ECCUses Hamming Code to Support 1-Bit ECCError Locator Module (ELM)Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH AlgorithmSupports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH AlgorithmsProgrammable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)Supports Protocols such as EtherCAT®, PROFIBUS®, PROFINET®, and EtherNet/IP™, EnDat 2.2, and MoreTwo Programmable Real-Time Units (PRUs) Subsystems With Two PRU Cores EachEach Core is a 32-Bit Load and Store RISC Processor Capable of Running at 200 MHz12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Instruction RAM With Single-Error Detection (Parity)8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Data RAM With Single-Error Detection (Parity)Single-Cycle 32-Bit Multiplier With 64-Bit AccumulatorEnhanced GPIO Module Provides Shift-In and Shift-Out Support and Parallel Latch on External Signal12KB (PRU-ICSS1 Only) of Shared RAM With Single-Error Detection (Parity)Three 120-Byte Register Banks Accessible by Each PRUInterrupt Controller Module (INTC) for Handling System Input EventsLocal Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSSPeripherals Inside the PRU-ICSSOne UART Port With Flow Control Pins, Supports up to 12 MbpsOne eCAP ModuleTwo MII Ethernet Ports that Support Industrial Ethernet, such as EtherCATOne MDIO PortIndustrial Communication is Supported by Two PRU-ICSS SubsystemsPower, Reset, and Clock Management (PRCM) ModuleControls the Entry and Exit of Deep-Sleep ModesResponsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On SequencingClocksIntegrated High-Frequency Oscillator Used to Generate a Reference Clock (19.2, 24, 25, and 26 MHz) for Various System and Peripheral ClocksSupports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power ConsumptionFive ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB, and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, and Ethernet)PowerTwo Nonswitchable Power Domains (RTC and Wake-Up Logic [WAKE-UP])Two Switchable Power Domains (MPU Subsystem, Peripherals and Infrastructure [PER])Dynamic Voltage Frequency Scaling (DVFS)Real-Time Clock (RTC)Real-Time Date (Day, Month, Year, and Day of Week) and Time (Hours, Minutes, and Seconds) InformationInternal 32.768-kHz Oscillator, RTC Logic, and 1.1-V Internal LDOIndependent Power-On-Reset (RTC_PWRONRSTn) InputDedicated Input Pin (RTC_WAKEUP) for External Wake EventsProgrammable Alarm Can Generate Internal Interrupts to the PRCM for Wakeup or Cortex-A9 for Event NotificationProgrammable Alarm Can Be Used With External Output (RTC_PMIC_EN) to Enable the Power-Management IC to Restore Non-RTC Power DomainsPeripheralsUp to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHYUp to Two Industrial Gigabit Ethernet MACs(10, 100, and 1000 Mbps)Integrated SwitchMAC Supports MII, RMII, and RGMII and MDIO InterfacesEthernet MAC and Switch Can Operate Independent of Other FunctionsIEEE 1588v2 Precision Time Protocol (PTP)Up to Two CAN PortsSupports CAN Version 2 Parts A and BUp to Two Multichannel Audio Serial Ports (McASPs)Transmit and Receive Clocks up to 50 MHzUp to Four Serial Data Pins Per McASP Port With Independent TX and RX ClocksSupports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar FormatsSupports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)FIFO Buffers for Transmit and Receive (256 Bytes)Up to Six UARTsAll UARTs Support IrDA and CIR ModesAll UARTs Support RTS and CTS Flow ControlUART1 Supports Full Modem ControlUp to Five Master and Slave McSPIsMcSPI0–McSPI2 Support up to Four Chip SelectsMcSPI3 and McSPI4 Support up to Two Chip SelectsUp to 48 MHzOne Quad-SPISupports eXecute In Place (XIP) from Serial NOR FLASHOne Dallas 1-Wire®and HDQ Serial InterfaceUp to Three MMC, SD, and SDIO Ports1-, 4-, and 8-Bit MMC, SD, and SDIO Modes1.8- or 3.3-V Operation on All PortsUp to 48-MHz ClockSupports Card Detect and Write ProtectComplies With MMC4.3 and SD and SDIO 2.0 SpecificationsUp to Three I2C Master and Slave InterfacesStandard Mode (up to 100 kHz)Fast Mode (up to 400 kHz)Up to Six Banks of General-Purpose I/O (GPIO)32 GPIOs per Bank (Multiplexed With Other Functional Pins)GPIOs Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)Up to Three External DMA Event Inputs That Can Also be Used as Interrupt InputsTwelve 32-Bit General-Purpose TimersDMTIMER1 is a 1-ms Timer Used for Operating System (OS) TicksDMTIMER4–DMTIMER7 are Pinned OutOne Public Watchdog TimerOne Free-Running, High-Resolution 32-kHz Counter (synctimer32K)Two 12-Bit SAR ADCs (ADC0, ADC1)867K Samples Per SecondInput Can Be Selected from Any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog SwitchUp to Three 32-Bit eCAP ModulesConfigurable as Three Capture Inputs or Three Auxiliary PWM OutputsUp to Six Enhanced eHRPWM ModulesDedicated 16-Bit Time-Base Counter With Time and Frequency ControlsConfigurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric OutputsUp to Three 32-Bit eQEP ModulesDevice IdentificationFactory Programmable Electrical Fuse Farm (FuseFarm)Production IDDevice Part Number (Unique JTAG ID)Device Revision (Readable by Host ARM)Debug Interface SupportJTAG and cJTAG for ARM (Cortex-A9 and PRCM) and PRU-ICSS DebugSupports Real-Time Trace Pins (for Cortex-A9)64-KB Embedded Trace Buffer (ETB)Supports Device Boundary ScanSupports IEEE 1500DMAOn-Chip Enhanced DMA Controller (EDMA) Has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA ChannelsEDMA is Used for:Transfers to and from On-Chip MemoriesTransfers to and from External Storage (EMIF, GPMC, and Slave Peripherals)InterProcessor Communication (IPC)Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between the Cortex-A9, PRCM, and PRU-ICSSBoot ModesBoot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input PinPackage491-Pin BGA Package (17-mm × 17-mm) (ZDN Suffix), 0.65-mm Ball Pitch With Via Channel Array Technology to Enable Low-Cost Routing

Description

AI
The TI AMIC120 high-performance processors are based on the ARM Cortex-A9 core. The processors are enhanced with a coprocessor for deterministic, real-time processing including industrial communication protocols, such as EtherCAT, PROFIBUS, EnDat, and others. The devices support high-level operating systems (HLOS). Linux®is available free of charge from TI. Other HLOSs are available from TI’s Design Network and ecosystem partners. These devices offer an upgrade to systems based on lower performance ARM cores and provide updated peripherals, including memory options such as QSPI-NOR and LPDDR2. The processors contain the subsystems shown in the Functional Block Diagram, and a brief description of each follows. The programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) is separate from the ARM core and allows independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, EnDat, and others. The PRU-ICSS enables EnDat and another industrial communication protocol in parallel. Additionally, the programmable nature of the PRU-ICSS, along with their access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in off-loading tasks from the other processor cores of the SoC. High-performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals. The device also offers a comprehensive clock-management scheme. One on-chip analog to digital converter (ADC1) can combine with the pulse width module to create a closed-loop motor control solution. The RTC provides a clock reference on a separate power domain. The clock reference enables a battery-backed clock reference. Cryptographic acceleration is available in every AMIC120 device. The TI AMIC120 high-performance processors are based on the ARM Cortex-A9 core. The processors are enhanced with a coprocessor for deterministic, real-time processing including industrial communication protocols, such as EtherCAT, PROFIBUS, EnDat, and others. The devices support high-level operating systems (HLOS). Linux®is available free of charge from TI. Other HLOSs are available from TI’s Design Network and ecosystem partners. These devices offer an upgrade to systems based on lower performance ARM cores and provide updated peripherals, including memory options such as QSPI-NOR and LPDDR2. The processors contain the subsystems shown in the Functional Block Diagram, and a brief description of each follows. The programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) is separate from the ARM core and allows independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, EnDat, and others. The PRU-ICSS enables EnDat and another industrial communication protocol in parallel. Additionally, the programmable nature of the PRU-ICSS, along with their access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in off-loading tasks from the other processor cores of the SoC. High-performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals. The device also offers a comprehensive clock-management scheme. One on-chip analog to digital converter (ADC1) can combine with the pulse width module to create a closed-loop motor control solution. The RTC provides a clock reference on a separate power domain. The clock reference enables a battery-backed clock reference. Cryptographic acceleration is available in every AMIC120 device.