LMK61E08 Series
Ultra-low jitter programmable oscillator with internal EEPROM
Manufacturer: Texas Instruments
Catalog
Ultra-low jitter programmable oscillator with internal EEPROM
Key Features
• Ultra-Low Noise, High PerformanceJitter: 90-fs RMS Typical fOUT> 100 MHz on LMK61E08PSRR: –70 dBc, Robust Supply Noise Immunity on LMK61E08Flexible Output Format on LMK61E08LVPECL up to 1 GHzLVDS up to 900 MHzHCSL up to 400 MHzTotal Frequency Tolerance of ±25 ppmSystem Level FeaturesGlitch-Less Frequency Margining: Up to ±1000 ppm From NominalInternal EEPROM: User Configurable Start-Up SettingsOther FeaturesDevice Control: Fast Mode I2C up to 1000 kHz3.3-V Operating VoltageIndustrial Temperature Range (–40ºC to +85ºC)7-mm × 5-mm 6-Pin PackageDefault Frequency:70.656 MHzUltra-Low Noise, High PerformanceJitter: 90-fs RMS Typical fOUT> 100 MHz on LMK61E08PSRR: –70 dBc, Robust Supply Noise Immunity on LMK61E08Flexible Output Format on LMK61E08LVPECL up to 1 GHzLVDS up to 900 MHzHCSL up to 400 MHzTotal Frequency Tolerance of ±25 ppmSystem Level FeaturesGlitch-Less Frequency Margining: Up to ±1000 ppm From NominalInternal EEPROM: User Configurable Start-Up SettingsOther FeaturesDevice Control: Fast Mode I2C up to 1000 kHz3.3-V Operating VoltageIndustrial Temperature Range (–40ºC to +85ºC)7-mm × 5-mm 6-Pin PackageDefault Frequency:70.656 MHz
Description
AI
The LMK61E08 family of ultra-low jitter PLLatinum™ programmable oscillators uses fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The output on LMK61E08 can be configured as LVPECL, LVDS, or HCSL. The device features self-start-up from on-chip EEPROM to generate a factory-programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through an I2C serial interface. The device provides fine and coarse frequency margining control through an I2C serial interface, making it a digitally-controlled oscillator (DCXO).
The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.
The LMK61E08 family of ultra-low jitter PLLatinum™ programmable oscillators uses fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The output on LMK61E08 can be configured as LVPECL, LVDS, or HCSL. The device features self-start-up from on-chip EEPROM to generate a factory-programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through an I2C serial interface. The device provides fine and coarse frequency margining control through an I2C serial interface, making it a digitally-controlled oscillator (DCXO).
The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.
