ADC12DJ800 Series

Dual-channel, 12-bit, 800-MSPS analog-to-digital converter (ADC) with JESD204C interface

Catalog

Dual-channel, 12-bit, 800-MSPS analog-to-digital converter (ADC) with JESD204C interface

Part	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Number of Bits	Architecture	Operating Temperature [Max]	Operating Temperature [Min]	Ratio - S/H:ADC	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]	Sampling Rate (Per Second)	Mounting Type	Supplier Device Package	Number of Inputs	Input Type	Package / Case	Data Interface	Configuration	Number of A/D Converters
Texas Instruments ADC12DJ800AAVT	1.05 V 1.8 V	1.15 V 2 V	12 bits	Pipelined SAR	85 °C	-40 °C	0:2	1.15 V	1.05 V	800 M	Surface Mount	144-FCBGA (10x10)	2	Differential	144-FBGA FCBGA	JESD204B/C	ADC	2
Texas Instruments ADC12DJ800AAV	1.05 V 1.8 V	1.15 V 2 V	12 bits	Pipelined SAR	85 °C	-40 °C	0:2	1.15 V	1.05 V	800 M	Surface Mount	144-FCBGA (10x10)	2	Differential	144-FBGA FCBGA	JESD204B/C	ADC	2

Catalog

Dual-channel, 12-bit, 800-MSPS analog-to-digital converter (ADC) with JESD204C interface

Key Features

• ADC Core:Resolution: 12 BitMaximum sampling rate: 800MSPSNon-interleaved architectureInternal dither reduces high-order harmonicsPerformance specifications (–1dBFS):SNR (97 MHz): 57.6dBFSENOB (97 MHz): 9 BitsSFDR (97 MHz): 62dBFSNoise floor (–20dBFS): –146.1dBFS/HzFull-scale input voltage: 800mVPP-DIFFFull-power input bandwidth: GHzJESD204C Serial data interface:Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanesMaximum baud-rate: 17.16Gbps64B/66B and 8B/10B encoding modesSubclass-1 support for deterministic latencyCompatible with JESD204B receiversOptional internal sampling clock generationInternal PLL and VCO (7.2–8.2GHz)SYSREF Windowing eases synchronizationFour clock outputs simplify system clockingReference clocks for FPGA or adjacent ADCReference clock for SerDes transceiversTimestamp input and output for pulsed systemsPower consumption (800MSPS):Quad Channel: 415mW / channelDual channel: 555mW / channelSingle channel: 830mWPower supplies: 1.1V, 1.9VADC Core:Resolution: 12 BitMaximum sampling rate: 800MSPSNon-interleaved architectureInternal dither reduces high-order harmonicsPerformance specifications (–1dBFS):SNR (97 MHz): 57.6dBFSENOB (97 MHz): 9 BitsSFDR (97 MHz): 62dBFSNoise floor (–20dBFS): –146.1dBFS/HzFull-scale input voltage: 800mVPP-DIFFFull-power input bandwidth: GHzJESD204C Serial data interface:Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanesMaximum baud-rate: 17.16Gbps64B/66B and 8B/10B encoding modesSubclass-1 support for deterministic latencyCompatible with JESD204B receiversOptional internal sampling clock generationInternal PLL and VCO (7.2–8.2GHz)SYSREF Windowing eases synchronizationFour clock outputs simplify system clockingReference clocks for FPGA or adjacent ADCReference clock for SerDes transceiversTimestamp input and output for pulsed systemsPower consumption (800MSPS):Quad Channel: 415mW / channelDual channel: 555mW / channelSingle channel: 830mWPower supplies: 1.1V, 1.9V

Description

ADC12xJ800 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800 ideally suited for a variety of multi-channel communications and test systems. Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. ADC12xJ800 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800 ideally suited for a variety of multi-channel communications and test systems. Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.