74HC4520D-Q100 Series

Dual 4-bit synchronous binary counter

Manufacturer: Freescale Semiconductor - NXP

Catalog

Dual 4-bit synchronous binary counter

Part	Number of Elements	Package / Case [x]	Package / Case	Package / Case [y]	Supplier Device Package	Trigger Type	Reset	Mounting Type	Count Rate	Operating Temperature [Max]	Operating Temperature [Min]	Logic Type	Number of Bits per Element	Timing	Direction	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case [custom]	Package / Case [custom]	Qualification	Grade
Freescale Semiconductor - NXP 74HC4520PW,118	2	0.173 in	16-TSSOP	4.4 mm	16-TSSOP	Negative Positive	Asynchronous	Surface Mount	69 MHz	125 °C	-40 °C	Binary Counter	4	Synchronous	Up	2 V	6 V
Freescale Semiconductor - NXP 74HC4520DB,112	2		16-SSOP		16-SSOP	Negative Positive	Asynchronous	Surface Mount	69 MHz	125 °C	-40 °C	Binary Counter	4	Synchronous	Up	2 V	6 V	0.209 in	5.3 mm
Freescale Semiconductor - NXP 74HC4520PW,112	2	0.173 in	16-TSSOP	4.4 mm	16-TSSOP	Negative Positive	Asynchronous	Surface Mount	69 MHz	125 °C	-40 °C	Binary Counter	4	Synchronous	Up	2 V	6 V
Freescale Semiconductor - NXP 74HC4520D-Q100J	2	0.154 in	16-SOIC	3.9 mm	16-SO	Negative Positive	Asynchronous	Surface Mount	69 MHz	125 °C	-40 °C	Binary Counter	4	Synchronous	Up	2 V	6 V			AEC-Q100	Automotive

Catalog

Dual 4-bit synchronous binary counter

Key Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• Wide supply voltage range from 2.0 V to 6.0 V

• CMOS low power dissipation

• High noise immunity

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Complies with JEDEC standards:

• JESD8C (2.7 V to 3.6 V)

• JESD7A (2.0 V to 6.0 V)

• Input levels:

• For 74HC4520-Q100: CMOS level

• For 74HCT4520-Q100: TTL level

• ESD protection:

• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

Description

The 74HC4520-Q100; 74HCT4520-Q100 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3), and an asynchronous master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of nCP0 when nCP1 is HIGH. It also advances on the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter. The other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.