ADS62P22 Series

Dual-Channel, 12-Bit, 65-MSPS Analog-to-Digital Converter (ADC)

Catalog

Dual-Channel, 12-Bit, 65-MSPS Analog-to-Digital Converter (ADC)

Part	Number of A/D Converters	Input Range	Sampling Rate (Per Second)	Data Interface	Power (Typ) @ Conditions	Number of Bits	Supplied Contents	Utilized IC / Part	Supplier Device Package	Architecture	Number of Inputs	Input Type	Ratio - S/H:ADC	Mounting Type	Voltage - Supply, Digital [Min]	Voltage - Supply, Digital [Max]	Features	Operating Temperature [Max]	Operating Temperature [Min]	Configuration	Voltage - Supply, Analog [Max]	Voltage - Supply, Analog [Min]	Package / Case	Reference Type
Texas Instruments ADS62P22EVM	1	2 Vpp	65 M	Parallel Serial	515 mW	12 bits	Board(s)	ADS62P22
Texas Instruments ADS62P22IRGCR	2		65 M	LVDS - Parallel Parallel		12 bits			64-VQFN (9x9)	Pipelined	2	Differential	1:1	Surface Mount	1.65 V	3.6 V	Simultaneous Sampling	85 °C	-40 °C	S/H-ADC	3.6 V	3 V	64-VFQFN Exposed Pad	External Internal
Texas Instruments ADS62P22IRGCT	2		65 M	LVDS - Parallel Parallel		12 bits			64-VQFN (9x9)	Pipelined	2	Differential	1:1	Surface Mount	1.65 V	3.6 V	Simultaneous Sampling	85 °C	-40 °C	S/H-ADC	3.6 V	3 V	64-VFQFN Exposed Pad	External Internal

Catalog

Dual-Channel, 12-Bit, 65-MSPS Analog-to-Digital Converter (ADC)

Key Features

• Maximum Sample Rate: 125 MSPS12-Bit Resolution with No Missing Codes95 dB CrosstalkParallel CMOS and DDR LVDS Output Options3.5 dB Coarse Gain and Programmable Fine Gainup to 6 dB for SNR/SFDR Trade-OffDigital Processing Blockwith:Offset CorrectionFine Gain Correction, in Steps of 0.05 dBDecimation by 2/4/8Built-in and Custom Programmable24-Tap Low-/High-/Band-Pass FiltersSupports Sine, LVPECL, LVDS, and LVCMOS Clocks andAmplitude Down to 400 mVPPClock Duty Cycle StabilizerInternal Reference; Supports External Reference also64-QFN Package (9mm × 9mm)Pin Compatible 14-Bit Family (ADS62P4X)Maximum Sample Rate: 125 MSPS12-Bit Resolution with No Missing Codes95 dB CrosstalkParallel CMOS and DDR LVDS Output Options3.5 dB Coarse Gain and Programmable Fine Gainup to 6 dB for SNR/SFDR Trade-OffDigital Processing Blockwith:Offset CorrectionFine Gain Correction, in Steps of 0.05 dBDecimation by 2/4/8Built-in and Custom Programmable24-Tap Low-/High-/Band-Pass FiltersSupports Sine, LVPECL, LVDS, and LVCMOS Clocks andAmplitude Down to 400 mVPPClock Duty Cycle StabilizerInternal Reference; Supports External Reference also64-QFN Package (9mm × 9mm)Pin Compatible 14-Bit Family (ADS62P4X)

Description

ADS62P2X is a dual channel 12-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. ADS62P2X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled. Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P2X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C). ADS62P2X is a dual channel 12-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. ADS62P2X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled. Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P2X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).