
Catalog
2-ch 500MSPS BTS Feedback and Receiver IC
Key Features
• Dual Channel12-Bit ResolutionMaximum Clock Rate: 500 MspsLow Swing Fullscale Input: 1.0 VppAnalog Input Buffer with High Impedance InputInput Bandwidth (3dB): >1.2GHzData Output Interface: DDR LVDS196-Pin BGA Package (12×12mm)Power Dissipation: 800mW/chPerformance at fin= 230 MHz IFSNR: 60.6 dBFSSFDR: 77 dBcPerformance at fin= 700 MHz IFSNR: 59.4 dBFSSFDR: 70 dBcReceive Mode: 2x Decimation with Low Pass orHigh Pass FilterFeedback Mode: Burst Mode Output for FullBandwidth DPD FeedbackDual Channel12-Bit ResolutionMaximum Clock Rate: 500 MspsLow Swing Fullscale Input: 1.0 VppAnalog Input Buffer with High Impedance InputInput Bandwidth (3dB): >1.2GHzData Output Interface: DDR LVDS196-Pin BGA Package (12×12mm)Power Dissipation: 800mW/chPerformance at fin= 230 MHz IFSNR: 60.6 dBFSSFDR: 77 dBcPerformance at fin= 700 MHz IFSNR: 59.4 dBFSSFDR: 70 dBcReceive Mode: 2x Decimation with Low Pass orHigh Pass FilterFeedback Mode: Burst Mode Output for FullBandwidth DPD Feedback
Description
AI
The ADS54T04 is a high linearity dual channel 12-bit, 500 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Two output modes are available for the output data – it can be decimated by two or the data can be output in burst mode. The burst mode output is designed specifically for DPD feedback applications where high resolution output data is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C).
The ADS54T04 is a high linearity dual channel 12-bit, 500 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Two output modes are available for the output data – it can be decimated by two or the data can be output in burst mode. The burst mode output is designed specifically for DPD feedback applications where high resolution output data is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C).