
SN74LVCH16244A Series
16-ch, 1.65-V to 3.6-V buffers with bus-hold and 3-state outputs
Manufacturer: Texas Instruments
Catalog
16-ch, 1.65-V to 3.6-V buffers with bus-hold and 3-state outputs
Key Features
• Member of the Texas InstrumentsWidebus FamilyOperates From 1.65 V to 3.6 VInputs Accept Voltages to 5.5 VMax tpdof 4.1 ns at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CIoffSupports Live Insertion, Partial-Power-DownMode, and Back-Drive ProtectionSupports Mixed-Mode Signal Operation on All Ports(5-V Input or Output Voltage With 3.3-V VCC)Bus Hold on Data Inputs Eliminates the Need forExternal Pullup or Pulldown ResistorsLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Member of the Texas InstrumentsWidebus FamilyOperates From 1.65 V to 3.6 VInputs Accept Voltages to 5.5 VMax tpdof 4.1 ns at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CIoffSupports Live Insertion, Partial-Power-DownMode, and Back-Drive ProtectionSupports Mixed-Mode Signal Operation on All Ports(5-V Input or Output Voltage With 3.3-V VCC)Bus Hold on Data Inputs Eliminates the Need forExternal Pullup or Pulldown ResistorsLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)
Description
AI
This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCCoperation. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.
The SN74LVCH16244A device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCCoperation. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.
The SN74LVCH16244A device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.