Catalog
Eight-bit voltage translating shift registers
Key Features
• Latching logic with known power-up state provides consistent start-up behaviorWide operating range of 1.65V to 5.5V5.5V tolerant input pinsLVxT enhanced inputs combined with open-drain outputs provide maximum voltage translation flexibility:Over 6.67Mbps operation, (RPU = 1kΩ,CL = 30pF)Up translation from 1.2V to 5V with 1.8V supplyDown translation from 5V to 0.8V or even less with any valid supplySupports standard function pinoutLatch-up performance exceeds 250mAper JESD 17Latching logic with known power-up state provides consistent start-up behaviorWide operating range of 1.65V to 5.5V5.5V tolerant input pinsLVxT enhanced inputs combined with open-drain outputs provide maximum voltage translation flexibility:Over 6.67Mbps operation, (RPU = 1kΩ,CL = 30pF)Up translation from 1.2V to 5V with 1.8V supplyDown translation from 5V to 0.8V or even less with any valid supplySupports standard function pinoutLatch-up performance exceeds 250mAper JESD 17
Description
AI
The SN74LV8T596 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel open-drain outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the outputs are in a high impedance state. The operation of the OE input does not impact the internal register data
The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
The SN74LV8T596 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel open-drain outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the outputs are in a high impedance state. The operation of the OE input does not impact the internal register data
The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
