TLC77-EP Series

The TLC77xx family of micropower supply voltage supervisors provide reset control, primarily in microcomputer and microprocessor systems. During power-on, RESET is asserted when VDDreaches 1 V. After minimum VDD(≥ 2 V) is established, the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI(SENSE)) remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure proper system reset. The delay time (td) is determined by an external capacitor: td= 2.1 × 104× CT Where CTis in farads tdis in seconds Except for the TLC7701, which can be customized with two external resistors, each supervisor has a fixed sense threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay time (td) has expired. In addition to the power-on reset and undervoltage-supervisor function, the TLC77xx adds power-down control support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure. By driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL driven by the memory bank select signal (CSH1) of the microprocessor (see ), the memory circuit is automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the battery.) The TLC77xx family of micropower supply voltage supervisors provide reset control, primarily in microcomputer and microprocessor systems. During power-on, RESET is asserted when VDDreaches 1 V. After minimum VDD(≥ 2 V) is established, the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI(SENSE)) remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure proper system reset. The delay time (td) is determined by an external capacitor: td= 2.1 × 104× CT Where CTis in farads tdis in seconds Except for the TLC7701, which can be customized with two external resistors, each supervisor has a fixed sense threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay time (td) has expired. In addition to the power-on reset and undervoltage-supervisor function, the TLC77xx adds power-down control support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure. By driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL driven by the memory bank select signal (CSH1) of the microprocessor (see ), the memory circuit is automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the battery.)