CD4034B Series

CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register

Catalog

CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register

Part	Voltage - Supply [Max]	Voltage - Supply [Min]	Number of Elements	Output Type	Package / Case [custom]	Package / Case	Package / Case [custom]	Operating Temperature [Min]	Operating Temperature [Max]	Supplier Device Package	Function	Number of Bits per Element	Mounting Type	Logic Type	Package / Case
Texas Instruments CD4034BM96G4	18 V	3 V	1	Push-Pull	7.5 mm	24-SOIC	0.295 in	-55 °C	125 °C	24-SOIC	Universal	8	Surface Mount	Register Bidirectional
Texas Instruments CD4034BM96E4	18 V	3 V	1	Push-Pull	7.5 mm	24-SOIC	0.295 in	-55 °C	125 °C	24-SOIC	Universal	8	Surface Mount	Register Bidirectional
Texas Instruments CD4034BPW	18 V	3 V	1	Push-Pull		24-TSSOP		-55 °C	125 °C	24-TSSOP	Universal	8	Surface Mount	Register Bidirectional	0.173 in 4.4 mm
Texas Instruments CD4034BM	18 V	3 V	1	Push-Pull	7.5 mm	24-SOIC	0.295 in	-55 °C	125 °C	24-SOIC	Universal	8	Surface Mount	Register Bidirectional

Catalog

CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register

Key Features

• Bidirectional parallel data inputParallel or serial inputs/parallel outputsAsynchronous or synchronous parallel data loadingParallel data-input enable on "A" data lines (3-state output)Data recirculation for register expansionMultipackage register expansionFully static operation dc-to-10 MHz (typ.) at VDD= 10 VStandardized, symmetrical output characteristics100% tested for quiescent current at 20 V5-V, 10-V, and 15-V parametric ratingsMaximum input current of 1 µA at 18 V over full package-temperature range; 100nA at 18 V and 25°CNoise margin (over full package-temperature range):1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 VMeets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"Applications:Parallel Input/Parallel Output, Serial Input/Parallel Output, Serial Input/Serial Output RegisterShift right/shift left registerShift right/shift left with parallel loadingAddress registerBuffer registerBus system register with enable parallel lines at bus sideDouble bus register systemUp-Down Johnson or ring counterPseudo-random code generatorsSample and hold register (storage, counting, display)Frequency and phase comparatorBidirectional parallel data inputParallel or serial inputs/parallel outputsAsynchronous or synchronous parallel data loadingParallel data-input enable on "A" data lines (3-state output)Data recirculation for register expansionMultipackage register expansionFully static operation dc-to-10 MHz (typ.) at VDD= 10 VStandardized, symmetrical output characteristics100% tested for quiescent current at 20 V5-V, 10-V, and 15-V parametric ratingsMaximum input current of 1 µA at 18 V over full package-temperature range; 100nA at 18 V and 25°CNoise margin (over full package-temperature range):1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 VMeets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"Applications:Parallel Input/Parallel Output, Serial Input/Parallel Output, Serial Input/Serial Output RegisterShift right/shift left registerShift right/shift left with parallel loadingAddress registerBuffer registerBus system register with enable parallel lines at bus sideDouble bus register systemUp-Down Johnson or ring counterPseudo-random code generatorsSample and hold register (storage, counting, display)Frequency and phase comparator

Description

CD4034B is a static eight-stage parallel-or serial-input parallel-output register. It can be used to: 1) bidirectionally transfer parallel information between two buses, 2) convert serial data to parallel form and direct the parallel data to either of two buses, 3) store (recirculate) parallel data, or 4) accept parallel data from either of two buses and convert that data to serial form. Input that control the operations include a single-phase CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/SERIAL (P/S). Data inputs include 16 bidirectional parallel data lines of which the eight A data lines are inputs (3-state outputs) and the B data lines are outputs (inputs) depending on the signal level on the A/B input. In addition, an input for SERIAL DATA is also provided. All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave. Isolation from external noise and the effects of loading is provided by output buffering. Register expansion can be accomplished by simply cascading CD4034B packages. The CD4034B types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (PW and PWR suffixes). CD4034B is a static eight-stage parallel-or serial-input parallel-output register. It can be used to: 1) bidirectionally transfer parallel information between two buses, 2) convert serial data to parallel form and direct the parallel data to either of two buses, 3) store (recirculate) parallel data, or 4) accept parallel data from either of two buses and convert that data to serial form. Input that control the operations include a single-phase CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/SERIAL (P/S). Data inputs include 16 bidirectional parallel data lines of which the eight A data lines are inputs (3-state outputs) and the B data lines are outputs (inputs) depending on the signal level on the A/B input. In addition, an input for SERIAL DATA is also provided. All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave. Isolation from external noise and the effects of loading is provided by output buffering. Register expansion can be accomplished by simply cascading CD4034B packages. The CD4034B types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (PW and PWR suffixes).