Catalog
LVDS 21-Bit Serializers/De-Serializers
Key Features
• Low power consumption
• 20 MHz to 85 MHz shift clock support
• 50% duty cycle on the clock output of receiver
• ±1V common-mode range around 1.2V
• Narrow bus reduces cable size and cost
• High throughput (up to 1.785 Gbps throughput)
• Up to 595 Mbps per channel
• Internal PLL with no external component
• Compatible with TIA/EIA-644 specification
• Devices are offered in 48-lead TSSOP packages
Description
AI
The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL (Low-Voltage TTL) data into three serial LVDS (Low-Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock, 21 bits of input LVTTL data are sampled and transmitted. The FIN1218 and FIN1216 receive and convert the three serial LVDS data streams back into 21 bits of LVTTL data. Table 1 provides a matrix summary of the serializers and de-serializers available. For the FIN1217, at a transmit clock frequency of 85MHz, 21 bits of LVTTL data are transmitted at a rate of 595Mbps per LVDS channel. These chipsets solve EMI and cable size problems associated with wide and high-speed TTL interfaces.
