ADC12D1620QML-SP Series

Radiation-hardness-assured (RHA), QMLV, 300-krad, 12-bit, dual 1.6-GSPS or single 3.2-GSPS ADC

Catalog

Radiation-hardness-assured (RHA), QMLV, 300-krad, 12-bit, dual 1.6-GSPS or single 3.2-GSPS ADC

Part	Number of A/D Converters	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Mounting Type	Input Type	Number of Inputs	Features	Sampling Rate (Per Second)	Data Interface	Configuration	Reference Type	Architecture	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]	Package / Case	Supplier Device Package	Ratio - S/H:ADC	Operating Temperature [Min]	Operating Temperature [Max]	Number of Bits
Texas Instruments ADC12D1620LGMPR	2	1.8 V	2 V	Surface Mount	Differential Single Ended	2	Simultaneous Sampling	3.2 G	LVDS - Parallel SPI	MUX-S/H-ADC	Internal	Folding Interpolating	2 V	1.8 V	256-BCLGA	256-CLGA (27.94x27.94)	0:1	-55 °C	125 °C	12 bits

Catalog

Radiation-hardness-assured (RHA), QMLV, 300-krad, 12-bit, dual 1.6-GSPS or single 3.2-GSPS ADC

Key Features

• Total ionizing dose (TID) to 300 krad(Si)Single event functional interrupt (SEFI) testedSingle event latch-up (SEL) > 120 MeV-cm2/mgCold sparing capableWide temperature range –55°C to +125°CPower consumption = 3.8 W or 2.7 W (1600- or 800-MHz clock)3-dB Input bandwidth = 3 GHzLow-sampling power-saving mode (LSPSM) reduces power consumption and improves performance for fCLK≤ 800 MHzAuto-sync function for multi-chip systemsTime stamp feature to capture external triggerTest patterns at output for system debug1:1 Non-demuxed or 1:2 or 1:4 parallel demuxed LVDS outputsSingle 1.9-V power supplyTotal ionizing dose (TID) to 300 krad(Si)Single event functional interrupt (SEFI) testedSingle event latch-up (SEL) > 120 MeV-cm2/mgCold sparing capableWide temperature range –55°C to +125°CPower consumption = 3.8 W or 2.7 W (1600- or 800-MHz clock)3-dB Input bandwidth = 3 GHzLow-sampling power-saving mode (LSPSM) reduces power consumption and improves performance for fCLK≤ 800 MHzAuto-sync function for multi-chip systemsTime stamp feature to capture external triggerTest patterns at output for system debug1:1 Non-demuxed or 1:2 or 1:4 parallel demuxed LVDS outputsSingle 1.9-V power supply

Description

The ADC12D1620QML uses a package redesign to achieve better ENOB, SNR, and X-talk compared to the ADC12D1600QML. As is its predecessor, the ADC12D1620QML is a low-power, high-performance CMOS analog-to-digital converter (ADC) that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual-channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a low-sampling power-saving mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS. The ADC12D1620QML uses a package redesign to achieve better ENOB, SNR, and X-talk compared to the ADC12D1600QML. As is its predecessor, the ADC12D1620QML is a low-power, high-performance CMOS analog-to-digital converter (ADC) that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual-channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a low-sampling power-saving mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS.