
TDA4VM-Q1 Series
Automotive system-on-a-chip for L2, L3 and near-field analytic systems using deep learning
Manufacturer: Texas Instruments
Catalog
Automotive system-on-a-chip for L2, L3 and near-field analytic systems using deep learning
Key Features
• Processor cores:C7x floating point, vector DSP, up to 1.0GHz, 80 GFLOPS, 256 GOPSDeep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0GHzVision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist acceleratorsDepth and Motion Processing Accelerators (DMPAC)Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz1MB shared L2 cache per dual-core Cortex-A72 cluster32KB L1 DCache and 48KB L1 ICache per Cortex-A72 coreSix Arm Cortex-R5F MCUs at up to 1.0GHz16K I-Cache, 16K D-Cache, 64K L2 TCMTwo Arm Cortex-R5F MCUs in isolated MCU subsystemFour Arm Cortex-R5F MCUs in general compute partitionTwo C66x floating point DSP, up to 1.35GHz, 40GFLOPS, 160GOPS3D GPU PowerVR Rogue 8XE GE8430, up to 750MHz, 96GFLOPS, 6Gpix/secCustom-designed interconnect fabric supporting near max processing entitlementMemory subsystem:Up to 8MB of on-chip L3 RAM with ECC and coherencyECC error protectionShared coherent cacheSupports internal DMA engineExternal Memory Interface (EMIF) module with ECCSupports LPDDR4 memory typesSupports speeds up to 4266MT/s32-bit data bus with inline ECCGeneral-Purpose Memory Controller (GPMC)512KB on-chip SRAM in MAIN domain, protected by ECCFunctional Safety:Functional Safety-Complianttargeted (on select part numbers)Developed for functional safety applicationsDocumentation will be available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL-D/SIL-3 targetedSystematic capability up to ASIL-D/SC-3 targetedHardware integrity up to ASIL-D/SIL-3 targeted for MCU DomainHardware integrity up to ASIL-B/SIL-2 targeted for Main DomainSafety-related certificationsISO 26262 certification up to ASIL-D by TÜV SÜD plannedIEC 61508 certification up to SIL-3 by TÜV SÜD plannedAEC-Q100 qualified on part number variants ending in Q1Device security (on select part numbers):Secure boot with secure run-time supportCustomer programmable root key, up to RSA-4K or ECC-512Embedded hardware security moduleCrypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DESHigh speed serial interfaces:Integrated Ethernet switch supporting up to 8 external portsAll ports support 2.5Gb SGMIIAll ports support 1Gb SGMII/RGMIIAll ports support 100Mb RMIIAny two ports support QSGMII (using 4 internal ports per QSGMII)Up to four PCI-Express (PCIe) Gen3 controllersUp to two lanes per controllerGen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiationTwo USB 3.0 dual-role device (DRD) subsystemTwo enhanced SuperSpeed Gen1 PortsEach port supports Type-C switchingEach port independently configurable as USB host, USB peripheral, or USB DRDAutomotive interfaces:Sixteen Modular Controller Area Network (MCAN) modules with full CAN-FD supportTwo CSI2.0 4L RX plus One CSI2.0 4L TX2.5Gbps RX throughput per lane (20Gbps total)Display subsystem:One eDP/DP interface with Multi-Display Support (MST)HDCP1.4/HDCP2.2 high-bandwidth digital content protectionOne DSI TX (up to 2.5K)Up to two DPIAudio interfaces:Twelve Multichannel Audio Serial Port (MCASP) modulesVideo acceleration:Ultra-HD video, one (3840 × 2160p, 60 fps), or two (3840 × 2160p, 30 fps) H.264/H.265 decodeFull-HD video, four (1920 × 1080p, 60 fps), or eight (1920 × 1080p, 30 fps) H.264/H.265 decodeFull-HD video, one (1920 × 1080p, 60 fps), or up to three (1920 × 1080p, 30 fps) H.264 encodeFlash memory interfaces:Embedded MultiMediaCard Interface ( eMMC™ 5.1)Universal Flash Storage (UFS 2.1) interface with two lanesTwo Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)Two simultaneous flash interfaces configured asOne OSPI and one QSPI flash interfacesor one HyperBus™ and one QSPI flash interfaceSystem-on-Chip (SoC) architecture:16-nm FinFET technology24 mm × 24 mm, 0.8-mm pitch, 827-pin FCBGA (ALF), enables IPC class 3 PCB routingTPS6594-Q1 Companion Power Management ICs (PMIC):Functional Safety support up to ASIL-DFlexible mapping to support different use casesProcessor cores:C7x floating point, vector DSP, up to 1.0GHz, 80 GFLOPS, 256 GOPSDeep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0GHzVision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist acceleratorsDepth and Motion Processing Accelerators (DMPAC)Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz1MB shared L2 cache per dual-core Cortex-A72 cluster32KB L1 DCache and 48KB L1 ICache per Cortex-A72 coreSix Arm Cortex-R5F MCUs at up to 1.0GHz16K I-Cache, 16K D-Cache, 64K L2 TCMTwo Arm Cortex-R5F MCUs in isolated MCU subsystemFour Arm Cortex-R5F MCUs in general compute partitionTwo C66x floating point DSP, up to 1.35GHz, 40GFLOPS, 160GOPS3D GPU PowerVR Rogue 8XE GE8430, up to 750MHz, 96GFLOPS, 6Gpix/secCustom-designed interconnect fabric supporting near max processing entitlementMemory subsystem:Up to 8MB of on-chip L3 RAM with ECC and coherencyECC error protectionShared coherent cacheSupports internal DMA engineExternal Memory Interface (EMIF) module with ECCSupports LPDDR4 memory typesSupports speeds up to 4266MT/s32-bit data bus with inline ECCGeneral-Purpose Memory Controller (GPMC)512KB on-chip SRAM in MAIN domain, protected by ECCFunctional Safety:Functional Safety-Complianttargeted (on select part numbers)Developed for functional safety applicationsDocumentation will be available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL-D/SIL-3 targetedSystematic capability up to ASIL-D/SC-3 targetedHardware integrity up to ASIL-D/SIL-3 targeted for MCU DomainHardware integrity up to ASIL-B/SIL-2 targeted for Main DomainSafety-related certificationsISO 26262 certification up to ASIL-D by TÜV SÜD plannedIEC 61508 certification up to SIL-3 by TÜV SÜD plannedAEC-Q100 qualified on part number variants ending in Q1Device security (on select part numbers):Secure boot with secure run-time supportCustomer programmable root key, up to RSA-4K or ECC-512Embedded hardware security moduleCrypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DESHigh speed serial interfaces:Integrated Ethernet switch supporting up to 8 external portsAll ports support 2.5Gb SGMIIAll ports support 1Gb SGMII/RGMIIAll ports support 100Mb RMIIAny two ports support QSGMII (using 4 internal ports per QSGMII)Up to four PCI-Express (PCIe) Gen3 controllersUp to two lanes per controllerGen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiationTwo USB 3.0 dual-role device (DRD) subsystemTwo enhanced SuperSpeed Gen1 PortsEach port supports Type-C switchingEach port independently configurable as USB host, USB peripheral, or USB DRDAutomotive interfaces:Sixteen Modular Controller Area Network (MCAN) modules with full CAN-FD supportTwo CSI2.0 4L RX plus One CSI2.0 4L TX2.5Gbps RX throughput per lane (20Gbps total)Display subsystem:One eDP/DP interface with Multi-Display Support (MST)HDCP1.4/HDCP2.2 high-bandwidth digital content protectionOne DSI TX (up to 2.5K)Up to two DPIAudio interfaces:Twelve Multichannel Audio Serial Port (MCASP) modulesVideo acceleration:Ultra-HD video, one (3840 × 2160p, 60 fps), or two (3840 × 2160p, 30 fps) H.264/H.265 decodeFull-HD video, four (1920 × 1080p, 60 fps), or eight (1920 × 1080p, 30 fps) H.264/H.265 decodeFull-HD video, one (1920 × 1080p, 60 fps), or up to three (1920 × 1080p, 30 fps) H.264 encodeFlash memory interfaces:Embedded MultiMediaCard Interface ( eMMC™ 5.1)Universal Flash Storage (UFS 2.1) interface with two lanesTwo Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)Two simultaneous flash interfaces configured asOne OSPI and one QSPI flash interfacesor one HyperBus™ and one QSPI flash interfaceSystem-on-Chip (SoC) architecture:16-nm FinFET technology24 mm × 24 mm, 0.8-mm pitch, 827-pin FCBGA (ALF), enables IPC class 3 PCB routingTPS6594-Q1 Companion Power Management ICs (PMIC):Functional Safety support up to ASIL-DFlexible mapping to support different use cases
Description
AI
The TDA4VM processor family targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in a functional safety compliant targeted architecture make the TDA4VM devices a great fit for several industrial applications, such as: Robotics, Machine Vision, Radar, and so on. The TDA4VM provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.
Key Performance Cores Overview
The "C7x" next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new "MMA" deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.
General Compute Cores and Integration Overview
Separate dual core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to six Arm Cortex-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm Cortex-A72’s unencumbered for applications. The integrated "8XE GE8430" GPU offers up to 100 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VM family also includes an MCU island eliminating the need for an external system microcontroller.
The TDA4VM processor family targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in a functional safety compliant targeted architecture make the TDA4VM devices a great fit for several industrial applications, such as: Robotics, Machine Vision, Radar, and so on. The TDA4VM provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.
Key Performance Cores Overview
The "C7x" next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new "MMA" deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.
General Compute Cores and Integration Overview
Separate dual core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to six Arm Cortex-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm Cortex-A72’s unencumbered for applications. The integrated "8XE GE8430" GPU offers up to 100 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VM family also includes an MCU island eliminating the need for an external system microcontroller.