Catalog
16-Bit Universal Bus Driver With 3-State Outputs
Key Features
• Member of the Texas Instruments Widebus™ FamilyOperates From 1.65 V to 3.6 VMax tpdof 3.2 ns at 3.3 V±24-mA Output Drive at 3.3 VIdeal for Use in PC100 Register DIMMDesigned to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM SpecificationLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Widebus is a trademark of Texas Instruments.Member of the Texas Instruments Widebus™ FamilyOperates From 1.65 V to 3.6 VMax tpdof 3.2 ns at 3.3 V±24-mA Output Drive at 3.3 VIdeal for Use in PC100 Register DIMMDesigned to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM SpecificationLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Widebus is a trademark of Texas Instruments.
Description
AI
This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE\) input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE\) input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
