AM3892 Series

Sitara processor: Arm Cortex-A8, HDMI

Catalog

Sitara processor: Arm Cortex-A8, HDMI

Part	Number of Cores/Bus Width	Speed	Mounting Type	Ethernet	Ethernet	Package / Case	Supplier Device Package	Operating Temperature [Max]	Display & Interface Controllers	Core Processor	Co-Processors/DSP	SATA	Additional Interfaces	Voltage - I/O	USB
Texas Instruments AM3892BCYG120	1 Core 32 Bit	1.2 GHz	Surface Mount	10 Mbps 100 Mbps 1000 Mbps	2	1031-BFBGA FCBGA	1031-FCBGA (25x25)	95 °C	HDMI HDVPSS	ARM® Cortex®-A8	Multimedia NEON™ SIMD	3 Gbps	I2C McASP McBSP SD/SDIO SPI UART	1.8 V 3.3 V	USB 2.0 + PHY (2)
Texas Instruments AM3892BCYG150	1 Core 32 Bit	1.5 GHz	Surface Mount	10 Mbps 100 Mbps 1000 Mbps	2	1031-BFBGA FCBGA	1031-FCBGA (25x25)	95 °C	HDMI HDVPSS	ARM® Cortex®-A8	Multimedia NEON™ SIMD	3 Gbps	I2C McASP McBSP SD/SDIO SPI UART	1.8 V 3.3 V	USB 2.0 + PHY (2)
Texas Instruments AM3892CCYG135	1 Core 32 Bit	1.35 GHz	Surface Mount	10 Mbps 100 Mbps 1000 Mbps	2	1031-BFBGA FCBGA	1031-FCBGA (25x25)	95 °C	HDMI HDVPSS	ARM® Cortex®-A8	Multimedia NEON™ SIMD	3 Gbps	I2C McASP McBSP SD/SDIO SPI UART	1.8 V 3.3 V	USB 2.0 + PHY (2)

Catalog

Sitara processor: Arm Cortex-A8, HDMI

Key Features

• High-Performance Sitara ARM Microprocessors (MPUs)ARMCortex-A8 RISC ProcessorUp to 1.20 GHzARM Cortex-A8 CoreARMv7 ArchitectureIn-Order, Dual-Issue, Superscalar Processor CoreNEON Multimedia ArchitectureSupports Integer and Floating Point (VFPv3-IEEE754 Compliant)Jazelle RCT Execution EnvironmentARM Cortex-A8 Memory Architecture32-KB Instruction and Data Caches256-KB L2 Cache64-KB RAM, 48-KB of Boot ROM512KB of On-Chip Memory Controller (OCMC) RAMSGX530 3D Graphics Engine (Available Only on the AM3894 Device)Delivers up to 30 MTriangles per SecondUniversal Scalable Shader EngineDirect3D Mobile, OpenGL ES 1.1 and 2.0, OpenVG 1.1, OpenMax API SupportAdvanced Geometry DMA Driven OperationProgrammable HQ Image Anti-AliasingEndiannessARM Instructions and Data – Little EndianHD Video Processing Subsystem (HDVPSS)Two 165-MHz HD Video Capture ChannelsOne 16-Bit or 24-Bit and One 16-Bit ChannelEach Channel Splittable Into Dual 8-Bit Capture ChannelsTwo 165-MHz HD Video Display ChannelsOne 16-Bit, 24-Bit, 30-Bit Channel and One 16-Bit ChannelSimultaneous SD and HD Analog OutputDigital HDMI 1.3 Transmitter with PHY with HDCP up to 165-MHz Pixel ClockThree Graphics LayersDual 32-Bit DDR2 and DDR3 SDRAM InterfacesSupports up to DDR2-800 and DDR3-1600Up to Eight x8 Devices Total2GB of Total Address SpaceDynamic Memory Manager (DMM)Programmable Multi-Zone Memory Mapping and InterleavingEnables Efficient 2D Block AccessesSupports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and MirroringOptimizes Interlaced AccessesOne PCI Express (PCIe) 2.0 Port with Integrated PHYSingle Port with 1 or 2 Lanes at 5.0 GT per SecondConfigurable as Root Complex or EndpointSerial ATA (SATA) 3.0 Gbps Controller with Integrated PHYsDirect Interface for Two Hard Disk DrivesHardware-Assisted Native Command Queuing (NCQ) from up to 32 EntriesSupports Port Multiplier and Command-Based SwitchingTwo 10 Mbps, 100 Mbps, and 1000 Mbps Ethernet MACs (EMAC)IEEE 802.3 Compliant (3.3-V I/O Only)MII and GMII Media Independent InterfacesManagement Data I/O (MDIO) ModuleDual USB 2.0 Ports with Integrated PHYsUSB 2.0 High-Speed and Full-Speed ClientUSB 2.0 High-Speed, Full-Speed, and Low-Speed HostSupports Endpoints 0-15General-Purpose Memory Controller (GPMC)8-Bit and 16-Bit Multiplexed Address and Data BusUp to 6 Chip Selects with up to 256-MB Address Space per Chip Select PinGlueless Interface to NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection), SRAM and Pseudo-SRAMError Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit and 512-Byte Hardware ECC for NANDFlexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICsEnhanced Direct-Memory-Access (EDMA) ControllerFour Transfer Controllers64 Independent DMA Channels and 8 Quick DMA (QDMA) ChannelsSeven 32-Bit General-Purpose TimersOne System Watchdog TimerThree Configurable UART, IrDA, and CIR ModulesUART0 with Modem Control SignalsSupports up to 3.6864 Mbps UARTSIR, MIR, FIR (4.0 MBAUD), and CIROne 40-MHz Serial Peripheral Interface (SPI) with Four Chip SelectsSD and SDIO Serial Interface (1-Bit and 4-Bit)Dual Inter-Integrated Circuit (I2C bus) PortsThree Multichannel Audio Serial Ports (McASPs)One Six-Serializer Transmit and Receive PortTwo Dual-Serializer Transmit and Receive PortsDIT-Capable For SDIF and PDIF (All Ports)Multichannel Buffered Serial Port (McBSP)Transmit and Receive Clocks up to 48 MHzTwo Clock Zones and Two Serial Data PinsSupports TDM, I2S, and Similar FormatsReal-Time Clock (RTC)One-Time or Periodic Interrupt GenerationUp to 64 General-Purpose I/O (GPIO) PinsOn-Chip ARM ROM Bootloader (RBL)Power, Reset, and Clock ManagementSmartReflex Technology (Level 2)Seven Independent Core Power DomainsClock Enable and Disable Control For Subsystems and PeripheralsIEEE 1149.1 (JTAG) and IEEE 1149.7 (cJTAG) CompatibleVia Channel Technology Enables use of0.8-mm Design Rules40-nm CMOS Technology3.3-V Single-Ended LVCMOS I/Os (Except for DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN at 1.8 V)High-Performance Sitara ARM Microprocessors (MPUs)ARMCortex-A8 RISC ProcessorUp to 1.20 GHzARM Cortex-A8 CoreARMv7 ArchitectureIn-Order, Dual-Issue, Superscalar Processor CoreNEON Multimedia ArchitectureSupports Integer and Floating Point (VFPv3-IEEE754 Compliant)Jazelle RCT Execution EnvironmentARM Cortex-A8 Memory Architecture32-KB Instruction and Data Caches256-KB L2 Cache64-KB RAM, 48-KB of Boot ROM512KB of On-Chip Memory Controller (OCMC) RAMSGX530 3D Graphics Engine (Available Only on the AM3894 Device)Delivers up to 30 MTriangles per SecondUniversal Scalable Shader EngineDirect3D Mobile, OpenGL ES 1.1 and 2.0, OpenVG 1.1, OpenMax API SupportAdvanced Geometry DMA Driven OperationProgrammable HQ Image Anti-AliasingEndiannessARM Instructions and Data – Little EndianHD Video Processing Subsystem (HDVPSS)Two 165-MHz HD Video Capture ChannelsOne 16-Bit or 24-Bit and One 16-Bit ChannelEach Channel Splittable Into Dual 8-Bit Capture ChannelsTwo 165-MHz HD Video Display ChannelsOne 16-Bit, 24-Bit, 30-Bit Channel and One 16-Bit ChannelSimultaneous SD and HD Analog OutputDigital HDMI 1.3 Transmitter with PHY with HDCP up to 165-MHz Pixel ClockThree Graphics LayersDual 32-Bit DDR2 and DDR3 SDRAM InterfacesSupports up to DDR2-800 and DDR3-1600Up to Eight x8 Devices Total2GB of Total Address SpaceDynamic Memory Manager (DMM)Programmable Multi-Zone Memory Mapping and InterleavingEnables Efficient 2D Block AccessesSupports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and MirroringOptimizes Interlaced AccessesOne PCI Express (PCIe) 2.0 Port with Integrated PHYSingle Port with 1 or 2 Lanes at 5.0 GT per SecondConfigurable as Root Complex or EndpointSerial ATA (SATA) 3.0 Gbps Controller with Integrated PHYsDirect Interface for Two Hard Disk DrivesHardware-Assisted Native Command Queuing (NCQ) from up to 32 EntriesSupports Port Multiplier and Command-Based SwitchingTwo 10 Mbps, 100 Mbps, and 1000 Mbps Ethernet MACs (EMAC)IEEE 802.3 Compliant (3.3-V I/O Only)MII and GMII Media Independent InterfacesManagement Data I/O (MDIO) ModuleDual USB 2.0 Ports with Integrated PHYsUSB 2.0 High-Speed and Full-Speed ClientUSB 2.0 High-Speed, Full-Speed, and Low-Speed HostSupports Endpoints 0-15General-Purpose Memory Controller (GPMC)8-Bit and 16-Bit Multiplexed Address and Data BusUp to 6 Chip Selects with up to 256-MB Address Space per Chip Select PinGlueless Interface to NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection), SRAM and Pseudo-SRAMError Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit and 512-Byte Hardware ECC for NANDFlexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICsEnhanced Direct-Memory-Access (EDMA) ControllerFour Transfer Controllers64 Independent DMA Channels and 8 Quick DMA (QDMA) ChannelsSeven 32-Bit General-Purpose TimersOne System Watchdog TimerThree Configurable UART, IrDA, and CIR ModulesUART0 with Modem Control SignalsSupports up to 3.6864 Mbps UARTSIR, MIR, FIR (4.0 MBAUD), and CIROne 40-MHz Serial Peripheral Interface (SPI) with Four Chip SelectsSD and SDIO Serial Interface (1-Bit and 4-Bit)Dual Inter-Integrated Circuit (I2C bus) PortsThree Multichannel Audio Serial Ports (McASPs)One Six-Serializer Transmit and Receive PortTwo Dual-Serializer Transmit and Receive PortsDIT-Capable For SDIF and PDIF (All Ports)Multichannel Buffered Serial Port (McBSP)Transmit and Receive Clocks up to 48 MHzTwo Clock Zones and Two Serial Data PinsSupports TDM, I2S, and Similar FormatsReal-Time Clock (RTC)One-Time or Periodic Interrupt GenerationUp to 64 General-Purpose I/O (GPIO) PinsOn-Chip ARM ROM Bootloader (RBL)Power, Reset, and Clock ManagementSmartReflex Technology (Level 2)Seven Independent Core Power DomainsClock Enable and Disable Control For Subsystems and PeripheralsIEEE 1149.1 (JTAG) and IEEE 1149.7 (cJTAG) CompatibleVia Channel Technology Enables use of0.8-mm Design Rules40-nm CMOS Technology3.3-V Single-Ended LVCMOS I/Os (Except for DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN at 1.8 V)

Description

The AM389x Sitara ARM processors are a highly integrated, programmable platform that leverages TI's Sitara technology to meet the processing needs of the following applications: single-board computing, network and communications processing, industrial automation, human machine interface, and interactive point-of-service kiosks. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device combines high-performance ARMprocessing with a highly integrated peripheral set. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache; and 64KB of RAM. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD video processing subsystem (HDVPSS), which provides output of simultaneous HD and SD analog video and dual HD video inputs; up to two Gigabit Ethernet MACs (10 Mbps,100, Mbps, 1000 Mbps) with GMII and MDIO interface; two USB ports with integrated 2.0 PHY; PCIe port x2 lanes GEN2 compliant interface, which allows the device to act as a PCIe root complex or device endpoint; one 6-channel McASP audio serial port (with DIT mode); two dual-channel McASP audio serial ports (with DIT mode); one McBSP multichannel buffered serial port; three UARTs with IrDA and CIR support; SPI serial interface; SD and SDIO serial interface; two I2C master and slave interfaces; up to 64 GPIO pins; seven 32-bit timers; system watchdog timer; dual DDR2 and DDR3 SDRAM interface; flexible 8-bit and 16-bit asynchronous memory interface; and up to two SATA interfaces for external storage on two disk drives or more with the use of a port multiplier. The device also includes an SGX530 3D graphics engine (available only on the AM3894 device) to off-load many video and imaging processing tasks from the core. Additionally, the device has a complete set of development tools for the ARM, including C compilers and a Microsoft Windows debugger interface for visibility into source code execution. The device package has been specially engineered with Via Channel technology. This technology allows use of 0.8-mm pitch PCB feature sizes in this 0.65-mm pitch package, and substantially reduces PCB costs. Via Channel technology also allows PCB routing in only two signal layers due to the increased layer efficiency of the Via Channel BGA technology. The AM389x Sitara ARM processors are a highly integrated, programmable platform that leverages TI's Sitara technology to meet the processing needs of the following applications: single-board computing, network and communications processing, industrial automation, human machine interface, and interactive point-of-service kiosks. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device combines high-performance ARMprocessing with a highly integrated peripheral set. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache; and 64KB of RAM. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD video processing subsystem (HDVPSS), which provides output of simultaneous HD and SD analog video and dual HD video inputs; up to two Gigabit Ethernet MACs (10 Mbps,100, Mbps, 1000 Mbps) with GMII and MDIO interface; two USB ports with integrated 2.0 PHY; PCIe port x2 lanes GEN2 compliant interface, which allows the device to act as a PCIe root complex or device endpoint; one 6-channel McASP audio serial port (with DIT mode); two dual-channel McASP audio serial ports (with DIT mode); one McBSP multichannel buffered serial port; three UARTs with IrDA and CIR support; SPI serial interface; SD and SDIO serial interface; two I2C master and slave interfaces; up to 64 GPIO pins; seven 32-bit timers; system watchdog timer; dual DDR2 and DDR3 SDRAM interface; flexible 8-bit and 16-bit asynchronous memory interface; and up to two SATA interfaces for external storage on two disk drives or more with the use of a port multiplier. The device also includes an SGX530 3D graphics engine (available only on the AM3894 device) to off-load many video and imaging processing tasks from the core. Additionally, the device has a complete set of development tools for the ARM, including C compilers and a Microsoft Windows debugger interface for visibility into source code execution. The device package has been specially engineered with Via Channel technology. This technology allows use of 0.8-mm pitch PCB feature sizes in this 0.65-mm pitch package, and substantially reduces PCB costs. Via Channel technology also allows PCB routing in only two signal layers due to the increased layer efficiency of the Via Channel BGA technology.