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71V65603

71V65603 Series

3.3V 256K X 36 ZBT Synchronous 3.3V I/O Pipelined SRAM

Catalog

3.3V 256K X 36 ZBT Synchronous 3.3V I/O Pipelined SRAM

Description

AI
The 71V65603 3.3V CMOS SRAM, organized as 256K X 36, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus, it has been given the name ZBT™, or Zero Bus Turnaround. The 71V65603 contains data I/O, address, and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.