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SN74CBTU4411

SN74CBTU4411 Series

2.5V, 4:1, 11-channel analog multiplexer suitable for DDR-II applications

Manufacturer: Texas Instruments

Catalog

2.5V, 4:1, 11-channel analog multiplexer suitable for DDR-II applications

Key Features

Supports SSTL_18 signaling levelsSuitable for DDR-II applicationsD-port outputs are precharged by bias voltage (VBIAS)Internal termination for control inputsHigh bandwidth (400 MHz minimum)Low and flat ON-state resistance (ron) characteristics, (ron= 17 Ω maximum)Internal 400-Ω pulldown resistorsLow differential and rising or falling edge skewLatch-up performance exceeds 100 mA per JESD 78, Class IISupports SSTL_18 signaling levelsSuitable for DDR-II applicationsD-port outputs are precharged by bias voltage (VBIAS)Internal termination for control inputsHigh bandwidth (400 MHz minimum)Low and flat ON-state resistance (ron) characteristics, (ron= 17 Ω maximum)Internal 400-Ω pulldown resistorsLow differential and rising or falling edge skewLatch-up performance exceeds 100 mA per JESD 78, Class II

Description

AI
The SN74CBTU4411 device is a high-bandwidth, SSTL_18 compatible FET multiplexer/demultiplexer with low ON-state resistance (ron). The device uses an internal charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ron. The low and flat ronallows for minimal propagation delay and supports rail-to-rail signaling on data input/output (I/O) ports. The device also features very low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Matched ronand I/O capacitance among channels results in extremely low differential and rising or falling edge skew. This allows the device to show optimal performance in DDR-II applications. The SN74CBTU4411 device is a high-bandwidth, SSTL_18 compatible FET multiplexer/demultiplexer with low ON-state resistance (ron). The device uses an internal charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ron. The low and flat ronallows for minimal propagation delay and supports rail-to-rail signaling on data input/output (I/O) ports. The device also features very low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Matched ronand I/O capacitance among channels results in extremely low differential and rising or falling edge skew. This allows the device to show optimal performance in DDR-II applications.