AM62A7-Q1 Series
2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras
Manufacturer: Texas Instruments
Catalog
2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras
Key Features
• Processor Cores:Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHzQuad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECCEach A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protectionSingle-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories512KB SRAM with SECDED ECCSingle-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memoriesDeep Learning Accelerator based on Single-core C7xC7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at 1.0GHzMatrix Multiply Accelerator (MMA), up to 2TOPS (8b) at 1.0GHz64KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection1.25MB of L2 SRAM with SECDED ECCVision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:315MPixel/s ISP; Up to 5MP @ 60fpsSupport for 12-bit RGB-IRSupport for up to 16-bit input RAW formatLine support up to 4096Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) supportOutput color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSLMultimedia:Display subsystemSingle display supportUp to 2048x1080 @ 60fpsUp to 165MHz pixel clock support with independent PLLDPI 24-bit RGB parallel interfaceSupports safety features such as freeze frame detection and MISR data checkOne Camera Serial interface (CSI-2) Receiver with 4-Lane D-PHYMIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2Support for 1,2,3 or 4 data lane mode up to 1.5Gbps per laneECC verification/correction with CRC check + ECC on RAMVirtual Channel support (up to 16)Ability to write stream data directly to DDR via DMAVideo Encoder/DecoderSupport for HEVC (H.265) Main profiles at Level 5.1 High-tierSupport for H.264 BaseLine/Main/High Profiles at Level 5.2Support for up to 4K UHD resolution (3840 × 2160)Clocking options supporting 240MPixels/s, 120MPixels/s, or 60MPixels/sMotion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)Memory Subsystem:Up to 2.29MB of On-chip RAM64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks256KB of On-Chip RAM with SECDED ECC in SMS Subsystem176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem1.25MB of L2 SRAM with SECDED ECC in C7x Deep Learning AcceleratorDDR Subsystem (DDRSS)Supports LPDDR432-bit data bus with inline ECCSupports speeds up to 3733MT/sMax addressable range of 8GBytesFunctional Safety:Functional Safety-Complianttargeted [Industrial]Developed for functional safety applicationsDocumentation will be available to aid IEC 61508 functional safety system designSystematic capability up to SIL 3 targetedHardware Integrity up to SIL 2 targetedSafety-related certificationIEC 61508 by TÜV SÜD plannedFunctional Safety-Complianttargeted [Automotive]Developed for functional safety applicationsDocumentation will be available to aid ISO 26262 functional safety system designSystematic capability up to ASIL D targetedHardware integrity up to ASIL B targetedSafety-related certificationISO 26262 by TÜV SÜD plannedAEC - Q100 qualified [Automotive]Security:Secure boot supportedHardware-enforced Root-of-Trust (RoT)Support to switch RoT via backup keySupport for takeover protection, IP protection, and anti-roll back protectionTrusted Execution Environment (TEE) supportedArm TrustZone based TEEExtensive firewall support for isolationSecure watchdog/timer/IPCSecure storage supportReplay Protected Memory Block (RPMB) supportDedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processingCryptographic acceleration supportedSession-aware cryptographic engine with ability to auto-switch key-material based on incoming data streamSupports cryptographic coresAES – 128-/192-/256-Bit key sizesSHA2 – 224-/256-/384-/512-Bit key sizesDRBG with true random number generatorPKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure bootDebugging securitySecure software controlled debug accessSecurity aware debuggingHigh-Speed Interfaces:Integrated Ethernet switch supporting (total 2 external ports)RMII(10/100) or RGMII (10/100/1000)IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)Clause 45 MDIO PHY managementPacket Classifier based on ALE engine with 512 classifiersPriority based flow controlTime Sensitive Networking (TSN) supportFour CPU H/W interrupt PacingIP/UDP/TCP checksum offload in hardwareTwo USB2.0 PortsPort configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)Integrated USB VBUS detectionGeneral Connectivity:9x Universal Asynchronous Receiver-Transmitters (UART)5x Serial Peripheral Interface (SPI) controllers6x Inter-Integrated Circuit (I2C) ports3x Multichannel Audio Serial Ports (McASP)Transmit and Receive Clocks up to 50MHzUp to 4/6/16 Serial Data Pins across 3x McASP with Independent TX and RX ClocksSupports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar FormatsSupports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)FIFO Buffers for Transmit and Receive (256 Bytes)Support for audio reference output clock3x enhanced PWM modules (ePWM)3x enhanced Quadrature Encoder Pulse modules (eQEP)3x enhanced Capture modules (eCAP)General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO3x Controller Area Network (CAN) modules with CAN-FD supportConforms w/ CAN Protocol 2.0 A, B and ISO 11898-1Full CAN FD support (up to 64 data bytes)Parity/ECC check for Message RAMSpeed up to 8MbpsMedia and Data Storage:3x Multi-Media Card/Secure Digital (MMC/SD/SDIO) interface1x 8-bit eMMC interface up to HS200 speed2x 4-bit SD/SDIO interface up to UHS-ICompliant with eMMC 5.1, SD 3.0, and SDIO Version 3.01× General-Purpose Memory Controller (GPMC) up to 133MHzFlexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)Uses BCH code to support 4-, 8-, or 16-bit ECCUses Hamming code to support 1-bit ECCError Locator Module (ELM)Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithmSupports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithmsOSPI/QSPI with DDR / SDR supportSupport for Serial NAND and Serial NOR Flash devices4GBytes memory address supportXIP mode with optional on-the-fly encryptionPower Management:Low-power modes supported by Device/Power ManagerPartial IO support for CAN/GPIO/UART wakeupDeepSleep : I/O + DDR (suspend to RAM)DeepSleepMCU OnlyStandbyDynamic frequency scaling for Cortex-A53Boot Options:UARTI2C EEPROMOSPI/QSPI FlashGPMC NOR/NAND FlashSerial NAND FlashSD CardeMMCUSB (host) boot from Mass Storage deviceUSB (device) boot from external host (DFU mode)EthernetTechnology / Package:16-nm FinFET technology18mm x 18mm, 0.8mm pitch full-array, 484-pin FCBGA (AMB)18mm x 18mm, 0.8mm pitch full-array, 484-pin FCCSP (ANF)Processor Cores:Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHzQuad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECCEach A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protectionSingle-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories512KB SRAM with SECDED ECCSingle-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memoriesDeep Learning Accelerator based on Single-core C7xC7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at 1.0GHzMatrix Multiply Accelerator (MMA), up to 2TOPS (8b) at 1.0GHz64KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection1.25MB of L2 SRAM with SECDED ECCVision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:315MPixel/s ISP; Up to 5MP @ 60fpsSupport for 12-bit RGB-IRSupport for up to 16-bit input RAW formatLine support up to 4096Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) supportOutput color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSLMultimedia:Display subsystemSingle display supportUp to 2048x1080 @ 60fpsUp to 165MHz pixel clock support with independent PLLDPI 24-bit RGB parallel interfaceSupports safety features such as freeze frame detection and MISR data checkOne Camera Serial interface (CSI-2) Receiver with 4-Lane D-PHYMIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2Support for 1,2,3 or 4 data lane mode up to 1.5Gbps per laneECC verification/correction with CRC check + ECC on RAMVirtual Channel support (up to 16)Ability to write stream data directly to DDR via DMAVideo Encoder/DecoderSupport for HEVC (H.265) Main profiles at Level 5.1 High-tierSupport for H.264 BaseLine/Main/High Profiles at Level 5.2Support for up to 4K UHD resolution (3840 × 2160)Clocking options supporting 240MPixels/s, 120MPixels/s, or 60MPixels/sMotion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)Memory Subsystem:Up to 2.29MB of On-chip RAM64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks256KB of On-Chip RAM with SECDED ECC in SMS Subsystem176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem1.25MB of L2 SRAM with SECDED ECC in C7x Deep Learning AcceleratorDDR Subsystem (DDRSS)Supports LPDDR432-bit data bus with inline ECCSupports speeds up to 3733MT/sMax addressable range of 8GBytesFunctional Safety:Functional Safety-Complianttargeted [Industrial]Developed for functional safety applicationsDocumentation will be available to aid IEC 61508 functional safety system designSystematic capability up to SIL 3 targetedHardware Integrity up to SIL 2 targetedSafety-related certificationIEC 61508 by TÜV SÜD plannedFunctional Safety-Complianttargeted [Automotive]Developed for functional safety applicationsDocumentation will be available to aid ISO 26262 functional safety system designSystematic capability up to ASIL D targetedHardware integrity up to ASIL B targetedSafety-related certificationISO 26262 by TÜV SÜD plannedAEC - Q100 qualified [Automotive]Security:Secure boot supportedHardware-enforced Root-of-Trust (RoT)Support to switch RoT via backup keySupport for takeover protection, IP protection, and anti-roll back protectionTrusted Execution Environment (TEE) supportedArm TrustZone based TEEExtensive firewall support for isolationSecure watchdog/timer/IPCSecure storage supportReplay Protected Memory Block (RPMB) supportDedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processingCryptographic acceleration supportedSession-aware cryptographic engine with ability to auto-switch key-material based on incoming data streamSupports cryptographic coresAES – 128-/192-/256-Bit key sizesSHA2 – 224-/256-/384-/512-Bit key sizesDRBG with true random number generatorPKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure bootDebugging securitySecure software controlled debug accessSecurity aware debuggingHigh-Speed Interfaces:Integrated Ethernet switch supporting (total 2 external ports)RMII(10/100) or RGMII (10/100/1000)IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)Clause 45 MDIO PHY managementPacket Classifier based on ALE engine with 512 classifiersPriority based flow controlTime Sensitive Networking (TSN) supportFour CPU H/W interrupt PacingIP/UDP/TCP checksum offload in hardwareTwo USB2.0 PortsPort configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)Integrated USB VBUS detectionGeneral Connectivity:9x Universal Asynchronous Receiver-Transmitters (UART)5x Serial Peripheral Interface (SPI) controllers6x Inter-Integrated Circuit (I2C) ports3x Multichannel Audio Serial Ports (McASP)Transmit and Receive Clocks up to 50MHzUp to 4/6/16 Serial Data Pins across 3x McASP with Independent TX and RX ClocksSupports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar FormatsSupports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)FIFO Buffers for Transmit and Receive (256 Bytes)Support for audio reference output clock3x enhanced PWM modules (ePWM)3x enhanced Quadrature Encoder Pulse modules (eQEP)3x enhanced Capture modules (eCAP)General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO3x Controller Area Network (CAN) modules with CAN-FD supportConforms w/ CAN Protocol 2.0 A, B and ISO 11898-1Full CAN FD support (up to 64 data bytes)Parity/ECC check for Message RAMSpeed up to 8MbpsMedia and Data Storage:3x Multi-Media Card/Secure Digital (MMC/SD/SDIO) interface1x 8-bit eMMC interface up to HS200 speed2x 4-bit SD/SDIO interface up to UHS-ICompliant with eMMC 5.1, SD 3.0, and SDIO Version 3.01× General-Purpose Memory Controller (GPMC) up to 133MHzFlexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)Uses BCH code to support 4-, 8-, or 16-bit ECCUses Hamming code to support 1-bit ECCError Locator Module (ELM)Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithmSupports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithmsOSPI/QSPI with DDR / SDR supportSupport for Serial NAND and Serial NOR Flash devices4GBytes memory address supportXIP mode with optional on-the-fly encryptionPower Management:Low-power modes supported by Device/Power ManagerPartial IO support for CAN/GPIO/UART wakeupDeepSleep : I/O + DDR (suspend to RAM)DeepSleepMCU OnlyStandbyDynamic frequency scaling for Cortex-A53Boot Options:UARTI2C EEPROMOSPI/QSPI FlashGPMC NOR/NAND FlashSerial NAND FlashSD CardeMMCUSB (host) boot from Mass Storage deviceUSB (device) boot from external host (DFU mode)EthernetTechnology / Package:16-nm FinFET technology18mm x 18mm, 0.8mm pitch full-array, 484-pin FCBGA (AMB)18mm x 18mm, 0.8mm pitch full-array, 484-pin FCCSP (ANF)
Description
AI
AM62Ax is an extension of the Sitara™ automotive-grade family of heterogeneous Arm® processors with embedded Deep Learning (DL), Video and Vision Processing acceleration, display interface and extensive automotive peripheral and networking options. AM62Ax is built for a set of cost-sensitive automotive applications including driver and in-cabin monitoring systems, next generation of eMirror system, as well as a broad set of industrial applications in Factory Automation, Building Automation, Robotics, and other markets. The cost optimized AM62Ax provides high-performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units (ECUs).
AM62Ax contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL) and video accelerators, a Cortex®-R5F MCU Channel core and a Cortex®-R5F Device Management core. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based-algorithms such as driver monitoring. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include the next generation C7000™ DSP from Texas Instruments ("C7x") with scalar and vector cores, dedicated "MMA" deep learning accelerator enabling performance up to 2 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.
The 3-port Gigabit Ethernet switch has one internal port and two external ports with TSN support and can be used to enable industrial networking options. In addition, an extensive peripherals set is included in AM62Ax to enable system level connectivity such as USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. AM62Ax supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and also employs advanced power management support for portable and power-sensitive applications.
AM62Ax is an extension of the Sitara™ automotive-grade family of heterogeneous Arm® processors with embedded Deep Learning (DL), Video and Vision Processing acceleration, display interface and extensive automotive peripheral and networking options. AM62Ax is built for a set of cost-sensitive automotive applications including driver and in-cabin monitoring systems, next generation of eMirror system, as well as a broad set of industrial applications in Factory Automation, Building Automation, Robotics, and other markets. The cost optimized AM62Ax provides high-performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units (ECUs).
AM62Ax contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL) and video accelerators, a Cortex®-R5F MCU Channel core and a Cortex®-R5F Device Management core. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based-algorithms such as driver monitoring. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include the next generation C7000™ DSP from Texas Instruments ("C7x") with scalar and vector cores, dedicated "MMA" deep learning accelerator enabling performance up to 2 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.
The 3-port Gigabit Ethernet switch has one internal port and two external ports with TSN support and can be used to enable industrial networking options. In addition, an extensive peripherals set is included in AM62Ax to enable system level connectivity such as USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. AM62Ax supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and also employs advanced power management support for portable and power-sensitive applications.