LMK04616 Series

Ultra low-noise and low power JESD204B compliant clock jitter cleaner

Catalog

Ultra low-noise and low power JESD204B compliant clock jitter cleaner

Part	Package / Case	Operating Temperature [Max]	Operating Temperature [Min]	Supplier Device Package	Mounting Type	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	PLL	Output	Input	Voltage - Supply [Max]	Voltage - Supply [Min]	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Number of Circuits	Divider/Multiplier	Frequency - Max [Max]	Type
Texas Instruments LMK04616ZCRR	144-LFBGA	85 °C	-40 °C	144-NFBGA (10x10)	Surface Mount	16	4		HCSL HSDS LVDS LVPECL	HCSL HSDS LCPECL LVCMOS LVDS LVPECL	3.465 V	1.7 V			1	Yes/No	2 GHz	Jitter Cleaner
Texas Instruments LMK04616ZCRT	144-LFBGA			144-NFBGA (10x10)	Surface Mount													Jitter Cleaner

Catalog

Ultra low-noise and low power JESD204B compliant clock jitter cleaner

Key Features

• Dual-loop PLL architectureUltra low noise (10 kHz to 20 MHz):48-fs RMS jitter at 1966.08 MHz50-fs RMS jitter at 983.04 MHz61-fs RMS jitter at 122.88 MHz–165-dBc/Hz noise floor at 122.88 MHzJESD204B supportSingle shot, pulsed, and continuous SYSREF16 differential output clocks in 8 frequency groupsProgrammable output swing between 700 mVpp to 1600 mVppEach output pair can be configured to SYSREF clock output16-bit channel dividerMinimum SYSREF frequency of 25 kHzMaximum output frequency of 2 GHzPrecision digital delay, dynamically adjustableDigital delay (DDLY) of ½ × clock distribution path frequency (2 GHz maximum)60-ps step analog delay50% duty cycle output divides, 1 to 65535(even and odd)Four reference inputsHoldover mode, when inputs are lostAutomatic and manual switch-over modesLoss-of-signal (LOS) detection1.05-W typical power consumption with 16 outputs activeOperates typically from a 1.8-V (outputs, inputs) and 3.3-V supply (digital, PLL1, PLL2_OSC, PLL2 core)Fully integrated programmable loop filterPLL2PLL2 phase detector rate up to 250 MHzOSCin frequency-doublerIntegrated low-noise VCOInternal power conditioning: better than –80 dBc PSRR on VDDO for 122.88-MHz differential outputs3- or 4-wire SPI interface (4-wire is default)–40ºC to +85ºC industrial ambient temperatureSupports 105ºC PCB temperature (measured at thermal pad)LMK04616: 10-mm × 10-mm NFBGA-144 package with 0.8-mm pitchDual-loop PLL architectureUltra low noise (10 kHz to 20 MHz):48-fs RMS jitter at 1966.08 MHz50-fs RMS jitter at 983.04 MHz61-fs RMS jitter at 122.88 MHz–165-dBc/Hz noise floor at 122.88 MHzJESD204B supportSingle shot, pulsed, and continuous SYSREF16 differential output clocks in 8 frequency groupsProgrammable output swing between 700 mVpp to 1600 mVppEach output pair can be configured to SYSREF clock output16-bit channel dividerMinimum SYSREF frequency of 25 kHzMaximum output frequency of 2 GHzPrecision digital delay, dynamically adjustableDigital delay (DDLY) of ½ × clock distribution path frequency (2 GHz maximum)60-ps step analog delay50% duty cycle output divides, 1 to 65535(even and odd)Four reference inputsHoldover mode, when inputs are lostAutomatic and manual switch-over modesLoss-of-signal (LOS) detection1.05-W typical power consumption with 16 outputs activeOperates typically from a 1.8-V (outputs, inputs) and 3.3-V supply (digital, PLL1, PLL2_OSC, PLL2 core)Fully integrated programmable loop filterPLL2PLL2 phase detector rate up to 250 MHzOSCin frequency-doublerIntegrated low-noise VCOInternal power conditioning: better than –80 dBc PSRR on VDDO for 122.88-MHz differential outputs3- or 4-wire SPI interface (4-wire is default)–40ºC to +85ºC industrial ambient temperatureSupports 105ºC PCB temperature (measured at thermal pad)LMK04616: 10-mm × 10-mm NFBGA-144 package with 0.8-mm pitch

Description

The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support. The 16 clock outputs can be configured to drive eight JESD204B converters or other logic devices using device and SYSREF clocks. The 17th output can be configured to provide a signal from PLL2 or a copy from the external VCXO. Features like fully integrated PLL1 and PLL2 loop filters, a high number of integrated LDOs, digital and analog delay, the flexibility to supply outputs with 3.3V, 2.5V and 1.8V as well as the option to generate multiple SYSREF domains simultaneously makes the device easy to use. Not limited to JESD204B applications each of the 17 outputs can be configured for traditional clocking systems. The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support. The 16 clock outputs can be configured to drive eight JESD204B converters or other logic devices using device and SYSREF clocks. The 17th output can be configured to provide a signal from PLL2 or a copy from the external VCXO. Features like fully integrated PLL1 and PLL2 loop filters, a high number of integrated LDOs, digital and analog delay, the flexibility to supply outputs with 3.3V, 2.5V and 1.8V as well as the option to generate multiple SYSREF domains simultaneously makes the device easy to use. Not limited to JESD204B applications each of the 17 outputs can be configured for traditional clocking systems.