
DS40MB200 Series
Dual 4.0-Gbps 2:1/1:2 CML mux/buffer with transmit pre-emphasis and receive equalization
Manufacturer: Texas Instruments
Catalog
Dual 4.0-Gbps 2:1/1:2 CML mux/buffer with transmit pre-emphasis and receive equalization
Key Features
• 1-Gbps to 4-Gbps Low Jitter OperationFixed Input EqualizationProgrammable Output Pre-EmphasisIndependent Switch and Line Side Pre-Emphasis ControlsProgrammable Switch-Side Loopback ModeOn-Chip Terminations3.3-V SupplyESD Rating of 6-kV HBM48-leadless WQFN Package (7 mm × 7 mm)0°C to +85°C Operating Temperature Range1-Gbps to 4-Gbps Low Jitter OperationFixed Input EqualizationProgrammable Output Pre-EmphasisIndependent Switch and Line Side Pre-Emphasis ControlsProgrammable Switch-Side Loopback ModeOn-Chip Terminations3.3-V SupplyESD Rating of 6-kV HBM48-leadless WQFN Package (7 mm × 7 mm)0°C to +85°C Operating Temperature Range
Description
AI
The DS40MB200 device is a dual signal conditioning 2:1 multiplexer (MUX) and 1:2 fan-out buffer designed for use in backplane-redundancy applications. Signal conditioning features include continuous time linear equalization (CTLE) and programmable output pre-emphasis, extending data communication in FR4 backplanes at rates up to 4 Gbps. Each input stage has a fixed equalizer to reduce intersymbol interference distortion from board traces.
All output drivers have four selectable steps of pre-emphasis to compensate for transmission losses from long FR4 backplanes and reduce deterministic jitter. The pre-emphasis levels can be independently controlled for the line-side and switch-side drivers. The internal loopback paths from switch-side input to switch-side output enable at-speed system testing. All receiver inputs are internally terminated with 100-Ω differential terminating resistors. All drivers are internally terminated with 50 Ω to VCC.
The DS40MB200 device is a dual signal conditioning 2:1 multiplexer (MUX) and 1:2 fan-out buffer designed for use in backplane-redundancy applications. Signal conditioning features include continuous time linear equalization (CTLE) and programmable output pre-emphasis, extending data communication in FR4 backplanes at rates up to 4 Gbps. Each input stage has a fixed equalizer to reduce intersymbol interference distortion from board traces.
All output drivers have four selectable steps of pre-emphasis to compensate for transmission losses from long FR4 backplanes and reduce deterministic jitter. The pre-emphasis levels can be independently controlled for the line-side and switch-side drivers. The internal loopback paths from switch-side input to switch-side output enable at-speed system testing. All receiver inputs are internally terminated with 100-Ω differential terminating resistors. All drivers are internally terminated with 50 Ω to VCC.