74AUP1G79GW Series

Low-power D-type flip-flop; positive-edge trigger

Catalog

Low-power D-type flip-flop; positive-edge trigger

Part	Supplier Device Package	Current - Quiescent (Iq)	Voltage - Supply [Min]	Voltage - Supply [Max]	Clock Frequency	Number of Bits per Element	Number of Elements	Type	Mounting Type	Input Capacitance	Package / Case	Output Type	Function	Max Propagation Delay @ V, Max CL	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Trigger Type	Operating Temperature [Max]	Operating Temperature [Min]
Nexperia USA Inc. 74AUP1G79GW,125	5-TSSOP	500 nA	0.8 V	3.6 V	309 MHz	1	1	D-Type	Surface Mount	0.8 pF	5-TSSOP SC-70-5 SOT-353	Non-Inverted	Standard	5.8 ns	4 mA	4 mA	Positive Edge	125 °C	-40 °C

Catalog

Low-power D-type flip-flop; positive-edge trigger

Description

The 74AUP1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCCrange from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFFcircuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.