SN74CBT16861 Series

5-V, 1:1 (SPST), 20-channel general-purpose FET bus switch with 2 control inputs

Catalog

5-V, 1:1 (SPST), 20-channel general-purpose FET bus switch with 2 control inputs

Part	Package / Case	Package / Case	Package / Case [custom]	Supplier Device Package	Independent Circuits	Type	Circuit	Circuit	Operating Temperature [Max]	Operating Temperature [Min]	Voltage Supply Source	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case [y]	Package / Case [y]
Texas Instruments SN74CBT16861DGGR	48-TFSOP	0.24 in	6.1 mm	48-TSSOP	2	Bus Switch	10	1:1	85 °C	-40 °C	Single Supply	Surface Mount	4.5 V	5.5 V
Texas Instruments SN74CBT16861DGVR	48-TFSOP	0.173 in 4.4 mm			2	Bus Switch	10	1:1	85 °C	-40 °C	Single Supply	Surface Mount	4.5 V	5.5 V
Texas Instruments SN74CBT16861DL	48-BSSOP			48-SSOP	2	Bus Switch	10	1:1	85 °C	-40 °C	Single Supply	Surface Mount	4.5 V	5.5 V	0.295 in	7.5 mm

Catalog

5-V, 1:1 (SPST), 20-channel general-purpose FET bus switch with 2 control inputs

Key Features

• Member of Texas Instruments' WidebusTMFamily5-Switch Connection Between Two PortsTTL-Compatible Input LevelsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIWidebus is a trademark of Texas Instruments.Member of Texas Instruments' WidebusTMFamily5-Switch Connection Between Two PortsTTL-Compatible Input LevelsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIWidebus is a trademark of Texas Instruments.

Description

The SN74CBT16861 provides 20 bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device is organized as one dual 10-bit switch with separate output-enable (OE\) input. When OE\ is low, the switch is on, and port A is connected to port B. When OE\ is high, the switch is open, and the high-impedance state exists between the two ports. The SN74CBT16861 provides 20 bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device is organized as one dual 10-bit switch with separate output-enable (OE\) input. When OE\ is low, the switch is on, and port A is connected to port B. When OE\ is high, the switch is open, and the high-impedance state exists between the two ports.