TL16C750E Series
Single UART with 64-Byte Fifos, Auto Flow Control, Low-Power Modes
Manufacturer: Texas Instruments
Catalog
Single UART with 64-Byte Fifos, Auto Flow Control, Low-Power Modes
Key Features
• Pin-to-Pin Compatible With the Existing TL16C550B/CProgrammable 16- or 64-Byte FIFOs to Reduce CPU InterruptsProgrammable Auto- RTS\ and Auto- CTS\In Auto- CTS\ Mode, CTS\ Controls TransmitterIn Auto- RTS\ Mode, Receiver FIFO Contents and Threshold Control RTS\Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power DropCapable of Running With All Existing TL16C450 SoftwareAfter Reset, All Registers Are Identical to the TL16C450 Register SetUp to 16-MHz Clock Rate for Up to 1-Mbaud OperationIn the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial DataProgrammable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216-1) and Generates an Internal 16 × ClockStandard Asynchronous Communication Bits (Start, Stop, and Parity) Added or Deleted to or From the Serial Data Stream5-V and 3-V OperationRegister Selectable Sleep Mode and Low-Power ModeIndependent Receiver Clock InputIndependently Controlled Transmit, Receive, Line Status, and Data Set InterruptsFully Programmable Serial Interface Characteristics:5-, 6-, 7-, or 8-Bit CharactersEven-, Odd-, or No-Parity Bit Generation and Detection1-, 11/2-, or 2-Stop Bit GenerationBaud Generation (DC to 1 Mbits Per Second)False Start Bit DetectionComplete Status Reporting Capabilities3-State Output CMOS Drive Capabilities for Bidirectional Data Bus and Control BusLine Break Generation and DetectionInternal Diagnostic Capabilities:Loopback Controls for Communications Link Fault IsolationBreak, Parity, Overrun, Framing Error SimulationFully Prioritized Interrupt System ControlsModem Control Functions ( CTS\, RTS\, DSR\, DTR\, RI\, and DCD\)Available in 44-Pin PLCC and 64-Pin SQFPIndustrial Temperature Range Available for 64-Pin SQFPTL16C750ASYNCHRONOUS COMMUNICATIONS ELEMENTWITH 64-BYTE FIFOs AND AUTOFLOW CONTROLSLLS191C - JANUARY 1995 - REVISED DECEMBER 1997Pin-to-Pin Compatible With the Existing TL16C550B/CProgrammable 16- or 64-Byte FIFOs to Reduce CPU InterruptsProgrammable Auto- RTS\ and Auto- CTS\In Auto- CTS\ Mode, CTS\ Controls TransmitterIn Auto- RTS\ Mode, Receiver FIFO Contents and Threshold Control RTS\Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power DropCapable of Running With All Existing TL16C450 SoftwareAfter Reset, All Registers Are Identical to the TL16C450 Register SetUp to 16-MHz Clock Rate for Up to 1-Mbaud OperationIn the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial DataProgrammable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216-1) and Generates an Internal 16 × ClockStandard Asynchronous Communication Bits (Start, Stop, and Parity) Added or Deleted to or From the Serial Data Stream5-V and 3-V OperationRegister Selectable Sleep Mode and Low-Power ModeIndependent Receiver Clock InputIndependently Controlled Transmit, Receive, Line Status, and Data Set InterruptsFully Programmable Serial Interface Characteristics:5-, 6-, 7-, or 8-Bit CharactersEven-, Odd-, or No-Parity Bit Generation and Detection1-, 11/2-, or 2-Stop Bit GenerationBaud Generation (DC to 1 Mbits Per Second)False Start Bit DetectionComplete Status Reporting Capabilities3-State Output CMOS Drive Capabilities for Bidirectional Data Bus and Control BusLine Break Generation and DetectionInternal Diagnostic Capabilities:Loopback Controls for Communications Link Fault IsolationBreak, Parity, Overrun, Framing Error SimulationFully Prioritized Interrupt System ControlsModem Control Functions ( CTS\, RTS\, DSR\, DTR\, RI\, and DCD\)Available in 44-Pin PLCC and 64-Pin SQFPIndustrial Temperature Range Available for 64-Pin SQFPTL16C750ASYNCHRONOUS COMMUNICATIONS ELEMENTWITH 64-BYTE FIFOs AND AUTOFLOW CONTROLSLLS191C - JANUARY 1995 - REVISED DECEMBER 1997
Description
AI
The TL16C750 is a functional upgrade of the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16C750, like the TL16C550C, can be placed in an alternate mode (FIFO mode). This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 64 bytes including three additional bits of error status per byte for the receiver FIFO. The user can choose between a 16-byte FIFO mode or an extended 64-byte FIFO mode. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow through the RTS\ output and the CTS\ input signals (see Figure 1).
The TL16C750 performs serial-to-parallel conversion on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The ACE includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.
The TL16C750 ACE includes a programmable baud rate generator capable of dividing a reference clock by divisors from 1 to (216- 1) and producing a 16× reference clock for the internal transmitter logic. Provisions are also included to use this 16× clock for the receiver logic. The ACE accommodates a 1-Mbaud serial rate (16-MHz input clock) so a bit time is 1 us and a typical character time is 10 us (start bit, 8 data bits, stop bit).
Two of the TL16C450 terminal functions have been changed to TXRDY\ and RXRDY\, which provide signaling to a direct memory access (DMA) controller.
The TL16C750 is a functional upgrade of the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16C750, like the TL16C550C, can be placed in an alternate mode (FIFO mode). This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 64 bytes including three additional bits of error status per byte for the receiver FIFO. The user can choose between a 16-byte FIFO mode or an extended 64-byte FIFO mode. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow through the RTS\ output and the CTS\ input signals (see Figure 1).
The TL16C750 performs serial-to-parallel conversion on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The ACE includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.
The TL16C750 ACE includes a programmable baud rate generator capable of dividing a reference clock by divisors from 1 to (216- 1) and producing a 16× reference clock for the internal transmitter logic. Provisions are also included to use this 16× clock for the receiver logic. The ACE accommodates a 1-Mbaud serial rate (16-MHz input clock) so a bit time is 1 us and a typical character time is 10 us (start bit, 8 data bits, stop bit).
Two of the TL16C450 terminal functions have been changed to TXRDY\ and RXRDY\, which provide signaling to a direct memory access (DMA) controller.
