74AUP1G32GZ Series

Low-power 2-input OR-gate

Catalog

Low-power 2-input OR-gate

Part	Package / Case	Number of Circuits	Logic Type	Mounting Type	Number of Inputs	Current - Quiescent (Max) [Max]	Supplier Device Package [y]	Supplier Device Package [x]	Supplier Device Package	Max Propagation Delay @ V, Max CL	Operating Temperature [Max]	Operating Temperature [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Input Logic Level - High [Max]	Input Logic Level - High [Min]	Voltage - Supply [Min]	Voltage - Supply [Max]
Nexperia USA Inc. 74AUP1G32GZYL	4-XDFN Exposed Pad	1	OR Gate	Surface Mount Wettable Flank	2	500 nA	0.85	1.1	5-XSON	6.4 ns	125 °C	-40 C	4 mA	4 mA	2 V	1.6 V	0.8 V	3.6 V

Catalog

Low-power 2-input OR-gate

Description

The 74AUP1G32 is a single 2-input OR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCCrange from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFFcircuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.