74LVT02D Series

3.3 V Quad 2-input NOR gate

Manufacturer: Freescale Semiconductor - NXP

Catalog

3.3 V Quad 2-input NOR gate

Part	Logic Type	Package / Case [x]	Package / Case [y]	Package / Case	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Supplier Device Package	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Min]	Voltage - Supply [Max]	Number of Inputs	Max Propagation Delay @ V, Max CL	Number of Circuits	Input Logic Level - Low	Mounting Type	Package / Case [custom]	Package / Case [custom]	Package / Case	Package / Case
Freescale Semiconductor - NXP 74LVT02D,112	NOR Gate	0.154 in	3.9 mm	14-SOIC	20 mA	32 mA	14-SO	85 °C	-40 °C	2.7 V	3.6 V	2	2.8 ns	4	0.8 V	Surface Mount
Freescale Semiconductor - NXP 74LVT02PW,112	NOR Gate			14-TSSOP	20 mA	32 mA	14-TSSOP	85 °C	-40 °C	2.7 V	3.6 V	2	2.8 ns	4	0.8 V	Surface Mount	0.173 "	4.4 mm
Freescale Semiconductor - NXP 74LVT02D,118	NOR Gate	0.154 in	3.9 mm	14-SOIC	20 mA	32 mA	14-SO	85 °C	-40 °C	2.7 V	3.6 V	2	2.8 ns	4	0.8 V	Surface Mount
Freescale Semiconductor - NXP 74LVT02DB,118	NOR Gate			14-SSOP	20 mA	32 mA	14-SSOP	85 °C	-40 °C	2.7 V	3.6 V	2	2.8 ns	4	0.8 V	Surface Mount			5.3 mm	0.209 "
Freescale Semiconductor - NXP 74LVT02PW,118	NOR Gate			14-TSSOP	20 mA	32 mA	14-TSSOP	85 °C	-40 °C	2.7 V	3.6 V	2	2.8 ns	4	0.8 V	Surface Mount	0.173 "	4.4 mm

Catalog

3.3 V Quad 2-input NOR gate

Key Features

• Wide supply voltage range from 2.7 V to 3.6 V

• Output capability: +64 mA and -32 mA

• Direct interface with TTL levels

• Overvoltage tolerant inputs to 5.5 V

• Power-up 3-state

• No bus current loading when output is tied to 5 V bus

• IOFFcircuitry provides partial Power-down mode operation

• Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

• Complies with JEDEC standards:

• JESD8C (2.7 V to 3.6 V)

• ESD protection:

• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

• Specified from -40 °C to 85 °C

Description

The 74LVT02 is a quad 2-input NOR gate. This device is fully specified for partial power down applications using IOFF. The IOFFcircuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.