AM2631-Q1 Series

Automotive single-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and security

Catalog

Automotive single-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and security

Part	Supplier Device Package	Speed	RAM Size	Peripherals	Program Memory Size	Package / Case	Data Converters	Number of I/O	Voltage - Supply (Vcc/Vdd) [Max]	Voltage - Supply (Vcc/Vdd) [Min]	Oscillator Type	Grade	Core Size	Operating Temperature [Max]	Operating Temperature [Min]	Core Processor	Mounting Type	Program Memory Type	Qualification
Texas Instruments AM2631CNDGHMZCZRQ1	324-NFBGA (15x15)	400 MHz	2 M	AES DMA POR PWM SHA TRNG WDT	256 KB	324-LFBGA	A/D 6x12b SAR D/A 1x12b	140	1.26 V	1.14 V	Internal	Automotive	32-Bit	150 °C	-40 °C	ARM® Cortex®-R5F	Surface Mount	Tightly Coupled Memory (TCM)	AEC-Q100

Catalog

Automotive single-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and security

Key Features

• Processor Cores:Single, dual, and quad-core Arm Cortex-R5F MCU with each core running up to 400 MHz16KB I-cache with 64-bit ECC per CPU core16KB D-cache with 32-bit ECC per CPU core64KB Tightly-Coupled Memory (TCM) with 32-bit ECC per CPU coreLockstep or Dual-core capable clustersMemory Subsystem:2MB of On-Chip RAM (OCSRAM)4 Banks x 512KBECC error protectionInternal DMA engine supportSystem on Chip (SoC) Services and Architecture:1x EDMA to support data movement functionsDevice Boot supported from the following interfaces:UART (Primary/Backup)QSPI NOR Flash (4S/1S) (Primary)Interprocessor communication modulesSPINLOCK module for synchronizing processes running on multiple coresMAILBOX functionality implemented through CTRLMMR registersCentral Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routersMedia and Data Storage:1x 4-bit Multi-Media Card/Secure Digital (MMC/SD) interfaceGeneral-Purpose Memory Controller (GPMC)16-bit parallel data bus with 22-bit address busUp to 4MB addressable memory spaceIntegrated Error Location Module (ELM) support for error checkingGeneral Connectivity:6x Universal Asynchronous RX-TX (UART)5x Serial Peripheral Interface (SPI) controllers5x Local Interconnect Network (LIN) ports4x Inter-Integrated Circuit (I2C) ports4x Modular Controller Area Network (MCAN) modules with CAN-FD support1x Quad Serial Peripheral Interface (QSPI)4x Fast Serial Interface Transmitters (FSITX)4x Fast Serial Interface Receivers (FSIRX)Up to 139 General-Purpose I/O (GPIO) pinsSensing & Actuation:Real-time Control Subsystem (CONTROLSS)Flexible Input/Output Crossbars (XBAR)5x 12-bit Analog-to-Digital Converters (ADC)6-input SAR ADC up to 4 MSPS6x Single-ended channels OR3x Differential channelsHighly Configurable ADC Digital LogicXBAR Start of Conversion Triggers (SOC)User-defined Sample and Hold (S+H)Flexible Post-Processing Blocks (PPB)10x Analog Comparators with Type-A programmable DAC reference (CMPSSA)10x Analog Comparators with Type-B programmable DAC reference (CMPSSB)1x 12-bit Digital-to-Analog Converter (DAC)32x Pulse Width Modulation (EPWM) modulesSingle or Dual PWM channelsAdvanced PWM ConfigurationsExtended HRPWM time resolution10x Enhanced Capture (ECAP) modules3x Enhanced Quadrature Encoder Pulse (EQEP) modules2x 4-Ch Sigma-Delta Filter Modules (SDFM)Additional Signal-multiplex Crossbars (XBAR)Industrial Connectivity:Programmable Real-Time Unit (PRU-SS) and PRU-Industrial Communication Subsystem (PRU-ICSS)Dual core Programmable Realtime Unit Subsystem (PRU0 / PRU1)Deterministic HardwareDynamic Firmware20-channel enhanced input (eGPI) per PRU20-channel enhanced output (eGPO) per PRUEmbedded Peripherals and Memory1x UART, 1x ECAP1x MDIO, 1x IEP,1x 32KB Shared General Purpose RAM2x 8KB Shared Data RAM1x 16KB IRAM per PRUScratchPad (SPAD), MAC/CRCDigital encoder and sigma-delta control loopsThe PRU-ICSS enables advanced industrial protocols including:EtherCAT, Ethernet/IP™,PROFINET, IO-Link for orderDedicated Interrupt Controller (INTC)Dynamic CONTROLSS XBAR IntegrationHigh-Speed Interfaces:Integrated Ethernet switch supporting two external portsRMII (10/100) or RGMII (10/100/1000)IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTPClause 45 MDIO PHY management512x ALE engine-based Packet ClassifiersPriority flow control with up to 2KB packet sizeFour CPU hardware interrupt pacingIP/UDP/TCP checksum offload in hardwareSecurity:Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITASecure boot supportDevice Take Over ProtectionHardware-enforced root-of-trustAuthenticated bootSW Anti-rollback protectionDebug securitySecure device debug only after proper authenticationAbility to disable device debug functionalityDevice ID and Key ManagementSupport for OTP Memory (FUSEROM)Store root keys & other security fieldsSeparate EFUSE controllers and FUSE ROMsUnique Public Device Identifiers (UIDs)Memory Protection Units (MPU)Dedicated Arm® MPU per Cortex®-R5F coreSystem MPU - present at various interfaces in the SoC (MPU or Firewall)8-16 Programmable RegionsEnable/Privilege IDStart/End AddressRead/Write/CachableSecure/Non-SecureCryptographic AccelerationCryptographic cores with DMA SupportAES - 128/192/256-bit key sizesSHA2 - 256/384/512-bit supportDRBG with pseudo and true random number generatorPKA (public key accelerator) to assist in RSA/ECC processingFunctional Safety:Enables design of systems with functional safety requirementsError Signaling Module (ESM) with designated SAFETY_ERRORn pinECC or parity on calculation-critical memoriesBuilt-In Self-Test (BIST) and fault-injection for CPU and on-chip RAMRuntime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checksFunctional Safety-Compliant[Industrial]Developed for functional safety applicationsDocumentation to be made available to aid IEC 61508 functional safety system designSystematic capability up to SIL-3Hardware integrity up to SIL-3Safety-related certificationIEC 61508 certified up to SIL-3 by TUV SUDFunctional Safety-Compliant[Automotive]Developed for functional safety applicationsDocumentation to be made available to aid ISO 26262 functional safety system designSystematic capability up to ASIL-DHardware integrity up to ASIL-DSafety-related certificationISO 26262 certified up to ASIL-D by TUV SUDTechnology / Package:AEC-Q100 qualified for automotive applications45-nm technologyZCZ Package324-pin NFBGA15.0 mm x 15.0 mm0.8 mm pitchProcessor Cores:Single, dual, and quad-core Arm Cortex-R5F MCU with each core running up to 400 MHz16KB I-cache with 64-bit ECC per CPU core16KB D-cache with 32-bit ECC per CPU core64KB Tightly-Coupled Memory (TCM) with 32-bit ECC per CPU coreLockstep or Dual-core capable clustersMemory Subsystem:2MB of On-Chip RAM (OCSRAM)4 Banks x 512KBECC error protectionInternal DMA engine supportSystem on Chip (SoC) Services and Architecture:1x EDMA to support data movement functionsDevice Boot supported from the following interfaces:UART (Primary/Backup)QSPI NOR Flash (4S/1S) (Primary)Interprocessor communication modulesSPINLOCK module for synchronizing processes running on multiple coresMAILBOX functionality implemented through CTRLMMR registersCentral Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routersMedia and Data Storage:1x 4-bit Multi-Media Card/Secure Digital (MMC/SD) interfaceGeneral-Purpose Memory Controller (GPMC)16-bit parallel data bus with 22-bit address busUp to 4MB addressable memory spaceIntegrated Error Location Module (ELM) support for error checkingGeneral Connectivity:6x Universal Asynchronous RX-TX (UART)5x Serial Peripheral Interface (SPI) controllers5x Local Interconnect Network (LIN) ports4x Inter-Integrated Circuit (I2C) ports4x Modular Controller Area Network (MCAN) modules with CAN-FD support1x Quad Serial Peripheral Interface (QSPI)4x Fast Serial Interface Transmitters (FSITX)4x Fast Serial Interface Receivers (FSIRX)Up to 139 General-Purpose I/O (GPIO) pinsSensing & Actuation:Real-time Control Subsystem (CONTROLSS)Flexible Input/Output Crossbars (XBAR)5x 12-bit Analog-to-Digital Converters (ADC)6-input SAR ADC up to 4 MSPS6x Single-ended channels OR3x Differential channelsHighly Configurable ADC Digital LogicXBAR Start of Conversion Triggers (SOC)User-defined Sample and Hold (S+H)Flexible Post-Processing Blocks (PPB)10x Analog Comparators with Type-A programmable DAC reference (CMPSSA)10x Analog Comparators with Type-B programmable DAC reference (CMPSSB)1x 12-bit Digital-to-Analog Converter (DAC)32x Pulse Width Modulation (EPWM) modulesSingle or Dual PWM channelsAdvanced PWM ConfigurationsExtended HRPWM time resolution10x Enhanced Capture (ECAP) modules3x Enhanced Quadrature Encoder Pulse (EQEP) modules2x 4-Ch Sigma-Delta Filter Modules (SDFM)Additional Signal-multiplex Crossbars (XBAR)Industrial Connectivity:Programmable Real-Time Unit (PRU-SS) and PRU-Industrial Communication Subsystem (PRU-ICSS)Dual core Programmable Realtime Unit Subsystem (PRU0 / PRU1)Deterministic HardwareDynamic Firmware20-channel enhanced input (eGPI) per PRU20-channel enhanced output (eGPO) per PRUEmbedded Peripherals and Memory1x UART, 1x ECAP1x MDIO, 1x IEP,1x 32KB Shared General Purpose RAM2x 8KB Shared Data RAM1x 16KB IRAM per PRUScratchPad (SPAD), MAC/CRCDigital encoder and sigma-delta control loopsThe PRU-ICSS enables advanced industrial protocols including:EtherCAT, Ethernet/IP™,PROFINET, IO-Link for orderDedicated Interrupt Controller (INTC)Dynamic CONTROLSS XBAR IntegrationHigh-Speed Interfaces:Integrated Ethernet switch supporting two external portsRMII (10/100) or RGMII (10/100/1000)IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTPClause 45 MDIO PHY management512x ALE engine-based Packet ClassifiersPriority flow control with up to 2KB packet sizeFour CPU hardware interrupt pacingIP/UDP/TCP checksum offload in hardwareSecurity:Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITASecure boot supportDevice Take Over ProtectionHardware-enforced root-of-trustAuthenticated bootSW Anti-rollback protectionDebug securitySecure device debug only after proper authenticationAbility to disable device debug functionalityDevice ID and Key ManagementSupport for OTP Memory (FUSEROM)Store root keys & other security fieldsSeparate EFUSE controllers and FUSE ROMsUnique Public Device Identifiers (UIDs)Memory Protection Units (MPU)Dedicated Arm® MPU per Cortex®-R5F coreSystem MPU - present at various interfaces in the SoC (MPU or Firewall)8-16 Programmable RegionsEnable/Privilege IDStart/End AddressRead/Write/CachableSecure/Non-SecureCryptographic AccelerationCryptographic cores with DMA SupportAES - 128/192/256-bit key sizesSHA2 - 256/384/512-bit supportDRBG with pseudo and true random number generatorPKA (public key accelerator) to assist in RSA/ECC processingFunctional Safety:Enables design of systems with functional safety requirementsError Signaling Module (ESM) with designated SAFETY_ERRORn pinECC or parity on calculation-critical memoriesBuilt-In Self-Test (BIST) and fault-injection for CPU and on-chip RAMRuntime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checksFunctional Safety-Compliant[Industrial]Developed for functional safety applicationsDocumentation to be made available to aid IEC 61508 functional safety system designSystematic capability up to SIL-3Hardware integrity up to SIL-3Safety-related certificationIEC 61508 certified up to SIL-3 by TUV SUDFunctional Safety-Compliant[Automotive]Developed for functional safety applicationsDocumentation to be made available to aid ISO 26262 functional safety system designSystematic capability up to ASIL-DHardware integrity up to ASIL-DSafety-related certificationISO 26262 certified up to ASIL-D by TUV SUDTechnology / Package:AEC-Q100 qualified for automotive applications45-nm technologyZCZ Package324-pin NFBGA15.0 mm x 15.0 mm0.8 mm pitch

Description

The AM263x Sitara™ Arm® Microcontrollers are built to meet the complex real-time processing needs of next generation industrial and automotive embedded products. The AM263x MCU family consists of multiple pin-to-pin compatible devices with up to four 400 MHz Arm® Cortex®-R5F cores. As an option, the Arm® R5F subsystem can be programmed to run in lockstep or dual-core mode for a multiple functional safety configurations. The industrial communications subsystem (PRU-ICSS) enables integrated industrial Ethernet communication protocols such as PROFINET®, TSN, Ethernet/IP®, EtherCAT® (among many others), standard Ethernet connectivity, and even custom I/O interfaces. The family is designed for the future of motor control and digital power applications with advanced analog sensing and digital actuation modules. The multiple R5F cores are arranged in cluster subsystems with 256KB of shared tightly coupled memory (TCM) along with 2MB of shared SRAM, greatly reducing the need for external memory. Extensive ECC is included for on-chip memories, peripherals, and interconnects for enhanced reliability. Granular firewalls managed by the Hardware Security Manager (HSM) enable developers to implement stringent security-minded system design requirements. Cryptographic acceleration and secure boot are also available on AM263x devices. TI provides a complete set of microcontroller software and development tools for the AM263x family of microcontrollers. The AM263x Sitara™ Arm® Microcontrollers are built to meet the complex real-time processing needs of next generation industrial and automotive embedded products. The AM263x MCU family consists of multiple pin-to-pin compatible devices with up to four 400 MHz Arm® Cortex®-R5F cores. As an option, the Arm® R5F subsystem can be programmed to run in lockstep or dual-core mode for a multiple functional safety configurations. The industrial communications subsystem (PRU-ICSS) enables integrated industrial Ethernet communication protocols such as PROFINET®, TSN, Ethernet/IP®, EtherCAT® (among many others), standard Ethernet connectivity, and even custom I/O interfaces. The family is designed for the future of motor control and digital power applications with advanced analog sensing and digital actuation modules. The multiple R5F cores are arranged in cluster subsystems with 256KB of shared tightly coupled memory (TCM) along with 2MB of shared SRAM, greatly reducing the need for external memory. Extensive ECC is included for on-chip memories, peripherals, and interconnects for enhanced reliability. Granular firewalls managed by the Hardware Security Manager (HSM) enable developers to implement stringent security-minded system design requirements. Cryptographic acceleration and secure boot are also available on AM263x devices. TI provides a complete set of microcontroller software and development tools for the AM263x family of microcontrollers.