MC100EP142 Series

ECL 9-Bit Shift Register

Catalog

ECL 9-Bit Shift Register

Part	Output Type	Number of Bits per Element	Package / Case	Function	Mounting Type	Supplier Device Package	Number of Elements	Logic Type	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Max]	Voltage - Supply [Min]	Output Type
ON Semiconductor MC100EP142MNG	Push-Pull	9	32-VFQFN Exposed Pad	Universal	Surface Mount	32-QFN (5x5)	1	Shift Register	85 °C	-40 °C	5.5 V	3 V
ON Semiconductor MC100EP142FAR2G	Push-Pull	9	32-LQFP	Universal	Surface Mount	32-LQFP (7x7)	1	Shift Register	85 °C	-40 °C	5.5 V	3 V
ON Semiconductor MC100EP142FAR2	Push-Pull	9	32-LQFP	Universal	Surface Mount	32-LQFP (7x7)	1	Shift Register	85 °C	-40 °C	5.5 V	3 V
ON Semiconductor MC100EP142MNR4G	Push-Pull	9	32-VFQFN Exposed Pad	Universal	Surface Mount	32-QFN (5x5)	1	Shift Register	85 °C	-40 °C	5.5 V	3 V
ON Semiconductor MC100EP142FA		9	32-LQFP	Universal	Surface Mount	32-LQFP (7x7)	1	Shift Register	85 °C	-40 °C	5.5 V	3 V	1.81 mOhm
ON Semiconductor MC100EP142FAG	Push-Pull	9	32-LQFP	Universal	Surface Mount	32-LQFP (7x7)	1	Shift Register	85 °C	-40 °C	5.5 V	3 V

Catalog

ECL 9-Bit Shift Register

Key Features

• > 3 GHz Minimum Shift Frequency

• 9-Bit for Byte-Parity Applications

• Asynchronous Master Reset

• Dual Clocks

• PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V

• NECL Mode Operating Range: VCC= 0 V with VEE= –3.0 V to –5.5 V

• Open Input Default State

• Safety Clamp on Inputs

Description

The MC10EP/100EP142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 - D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.The SEL (Select) input pin is used to switch between the two modes of operation - SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK0 or CLK1; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the resisters to zero.The 100 Series contains temperature compensation.