DS92LV0412 Series

5 - 50 MHz Channel Link II Deserializer with LVDS Parallel Interface

Catalog

5 - 50 MHz Channel Link II Deserializer with LVDS Parallel Interface

Part	Function	Mounting Type	Supplier Device Package	Voltage - Supply [Max]	Voltage - Supply [Min]	Number of Inputs	Operating Temperature [Max]	Operating Temperature [Min]	Number of Outputs	Data Rate	Input Type	Output Type	Package / Case
Texas Instruments DS92LV0412SQE/NOPB	Deserializer	Surface Mount	48-WQFN (7x7)	1.89 V 3.6 V	1.71 V 3 V	1	85 °C	-40 °C	5	1.4 Gbps	CML	LVDS	48-WFQFN Exposed Pad

Catalog

5 - 50 MHz Channel Link II Deserializer with LVDS Parallel Interface

Key Features

• 5-Channel (4 data + 1 clock) Channel Link LVDS Parallel Interface Supports 24-bit Data3-bit Control at 5 – 50 MHzAC Coupled STP Interconnect up to 10 Meters in LengthIntegrated Serial CML TerminationsAT–SPEED BIST Mode and Status PinOptional I2C Compatible Serial Control BusPower Down Mode Minimizes Power Dissipation1.8V or 3.3V Compatible Control Pin Interface>8 kV ESD (HBM) Protection-40° to +85°C Temperature RangeSERIALIZER – DS92LV0411Data Scrambler for Reduced EMIDC–Balance Encoder for AC CouplingSelectable Output VOD and Adjustable De-EmphasisDESERIALIZER – DS92LV0412Random Data Lock; No Reference Clock RequiredAdjustable Input Receiver EqualizationEMI Minimization on Output Parallel Bus (Spread Spectrum Clock Generation and LVDS VOD Select)All trademarks are the property of their respective owners.5-Channel (4 data + 1 clock) Channel Link LVDS Parallel Interface Supports 24-bit Data3-bit Control at 5 – 50 MHzAC Coupled STP Interconnect up to 10 Meters in LengthIntegrated Serial CML TerminationsAT–SPEED BIST Mode and Status PinOptional I2C Compatible Serial Control BusPower Down Mode Minimizes Power Dissipation1.8V or 3.3V Compatible Control Pin Interface>8 kV ESD (HBM) Protection-40° to +85°C Temperature RangeSERIALIZER – DS92LV0411Data Scrambler for Reduced EMIDC–Balance Encoder for AC CouplingSelectable Output VOD and Adjustable De-EmphasisDESERIALIZER – DS92LV0412Random Data Lock; No Reference Clock RequiredAdjustable Input Receiver EqualizationEMI Minimization on Output Parallel Bus (Spread Spectrum Clock Generation and LVDS VOD Select)All trademarks are the property of their respective owners.

Description

The DS92LV0411 (serializer) and DS92LV0412 (deserializer) chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized interface over a single CML pair. The DS92LV0411/DS92LV0412 enables applications that currently use the popular Channel Link or Channel Link style devices to seamlessly upgrade to an embedded clock interface to reduce interconnect cost or ease design challenges. The parallel LVDS interface also reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces. Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables longer distance transmission over lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing easy "plug-and-go" operation. The DS92LV0411 and DS92LV0412 are programmable though an I2C interface as well as by pins. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics. The DS92LV0411 and DS92LV0412 can be used interchangeably with the DS92LV2411 or DS92LV2412. This allows designers the flexibility to connect to the host device and receiving devices with different interface types, LVDS or LVCMOS. The DS92LV0411 (serializer) and DS92LV0412 (deserializer) chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized interface over a single CML pair. The DS92LV0411/DS92LV0412 enables applications that currently use the popular Channel Link or Channel Link style devices to seamlessly upgrade to an embedded clock interface to reduce interconnect cost or ease design challenges. The parallel LVDS interface also reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces. Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables longer distance transmission over lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing easy "plug-and-go" operation. The DS92LV0411 and DS92LV0412 are programmable though an I2C interface as well as by pins. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics. The DS92LV0411 and DS92LV0412 can be used interchangeably with the DS92LV2411 or DS92LV2412. This allows designers the flexibility to connect to the host device and receiving devices with different interface types, LVDS or LVCMOS.