AM6442 Series

Dual-core 64-bit Arm® Cortex®-A53, quad-core Cortex-R5F, PCIe, USB 3.0 and security

Catalog

Dual-core 64-bit Arm® Cortex®-A53, quad-core Cortex-R5F, PCIe, USB 3.0 and security

Part	RAM Controllers	Mounting Type	Security Features	Voltage - I/O	USB	Number of Cores/Bus Width	Co-Processors/DSP	Ethernet	Additional Interfaces	Package / Case	Operating Temperature [custom]	Supplier Device Package	Core Processor	Speed	Speed	Speed
Texas Instruments AM6442BSEFHAALV	DDR4 LPDDR4	Surface Mount	3DES AES Cryptography DES MD5 Secure Boot SHA-1/2	1.1 V 1.2 V 1.8 V 3.3 V	USB 3.1 (1)	7 Core 64 Bit	Multimedia NEON™ SIMD	10/100 Mbps (2) 10/100/1000 Mbps (2)	CANbus GPIO I2C PCI QSPI SPI UART	441-BFBGA FCBGA	-40 °C 105 °C	441-FCBGA (17.2x17.2)	ARM® Cortex®-A53 ARM® Cortex®-M5F ARM® Cortex®-R5F	1 GHz	800 MHz	400 MHz
Texas Instruments AM6442BSDGHAALV	DDR4 LPDDR4	Surface Mount	3DES AES ARM TZ Cryptography DRBG ECC MD5 PKA Random Number Generator RSA Secure Boot SHA-1/2	1.1 V 1.2 V 1.8 V 3.3 V	USB 3.1 (1)	7 Core 64 Bit	ARM® Cortex®-M4F ARM® Cortex®-R5F Multimedia NEON™ SIMD PRU-ICSS	10/100 Mbps (2) 10/100/1000 Mbps (2)	CANbus DMA GPIO I2C MMC/SD PCIe QSPI SPI UART/USART	441-BFBGA FCBGA	-40 °C 105 °C	441-FCBGA (17.2x17.2)	ARM® Cortex®-A53 ARM® Cortex®-M5F ARM® Cortex®-R5F	1 GHz
Texas Instruments AM6442BSEGHAALV	DDR4 LPDDR4	Surface Mount	3DES AES ARM TZ Cryptography DRBG ECC MD5 PKA Random Number Generator RSA Secure Boot SHA-1/2	1.1 V 1.2 V 1.8 V 3.3 V	USB 3.1 (1)	2 Core 64 Bit	ARM® Cortex®-M4F ARM® Cortex®-R5F Multimedia NEON™ SIMD PRU-ICSS	10/100 Mbps (2) 10/100/1000 Mbps (2)	CANbus DMA GPIO I2C MMC/SD PCIe QSPI SPI UART/USART	441-BFBGA FCBGA	-40 °C 105 °C	441-FCBGA (17.2x17.2)	ARM® Cortex®-A53 ARM® Cortex®-M5F ARM® Cortex®-R5F	1 GHz
Texas Instruments AM6442BSFGHAALV	DDR4 LPDDR4	Surface Mount	3DES AES ARM TZ Cryptography DRBG ECC MD5 PKA Random Number Generator RSA Secure Boot SHA-1/2	1.1 V 1.2 V 1.8 V 3.3 V	USB 3.1 (1)	7 Core 64 Bit	ARM® Cortex®-M4F ARM® Cortex®-R5F Multimedia NEON™ SIMD PRU-ICSS	10/100 Mbps (2) 10/100/1000 Mbps (2)	CANbus DMA GPIO I2C MMC/SD PCIe QSPI SPI UART/USART	441-BFBGA FCBGA	-40 °C 105 °C	441-FCBGA (17.2x17.2)	ARM® Cortex®-A53 ARM® Cortex®-M5F ARM® Cortex®-R5F	1 GHz
Texas Instruments AM6442BSFFHAALV	DDR4 LPDDR4	Surface Mount	3DES AES ARM TZ Cryptography DRBG ECC MD5 PKA Random Number Generator RSA Secure Boot SHA-1/2	1.1 V 1.2 V 1.8 V 3.3 V	USB 3.1 (1)	7 Core 64 Bit	ARM® Cortex®-M4F ARM® Cortex®-R5F Multimedia NEON™ SIMD PRU-ICSS	10/100 Mbps (2) 10/100/1000 Mbps (2)	CANbus DMA GPIO I2C MMC/SD PCIe QSPI SPI UART/USART	441-BFBGA FCBGA	-40 °C 105 °C	441-FCBGA (17.2x17.2)	ARM® Cortex®-A53 ARM® Cortex®-M5F ARM® Cortex®-R5F	1 GHz

Catalog

Dual-core 64-bit Arm® Cortex®-A53, quad-core Cortex-R5F, PCIe, USB 3.0 and security

Key Features

• Processor cores:1× Dual 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.0GHzDual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECCEach A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protectionUp to 2× Dual-core Arm Cortex-R5F MCU subsystems at up to 800MHz, integrated for real-time processingDual-core Arm Cortex-R5F supports dual-core and single-core modes32KB ICache, 32KB DCache and 64KB TCM per each R5F core for a total of 256KB TCM with SECDED ECC on all memories1× Single-core Arm Cortex-M4F MCU at up to 400MHz256KB SRAM with SECDED ECCIndustrial subsystem:2× gigabit Industrial Communication Subsystems (PRU_ICSSG)Supports Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and moreBackward compatibility with 10/100Mb PRU_ICSSEach PRU_ICSSG contains:2× Ethernet portsMII (10/100)RGMII (10/100/1000)6 PRU RISC cores per PRU_ICSSG each core having:Instruction RAM with ECCBroadside RAMMultiplier with optional accumulator (MAC)CRC16/32 hardware acceleratorByte swap for Big/Little Endian conversionSUM32 hardware accelerator for UDP checksumTask Manager for preemption supportThree Data RAMs with ECC8 banks of 30 × 32-bit register scratchpad memoryInterrupt controller and task managerTwo 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions18× Sigma-Delta filtersShort circuit logicOver-current logic6× Multi-protocol position encoder interfacesOne Enhanced Capture Module (ECAP)16550-compatible UART with a dedicated 192-MHz clock to support 12-Mbps PROFIBUSMemory subsystem:Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banksEach memory bank can be allocated to a single core to facilitate software task partitioningDDR Subsystem (DDRSS)Supports LPDDR4, DDR4 memory types16-Bit data bus with inline ECCSupports speeds up to 1600MT/s1× General-Purpose Memory Controller (GPMC)16-Bit parallel bus with 133-MHz clock or32-Bit parallel bus with 100-MHz clockError Location Module (ELM) supportSystem on Chip (SoC) Services:Device Management Security Controller (DMSC-L)Centralized SoC system controllerManages system services including initial boot, security, and clock/reset/power managementCommunication with various processing units over message managerSimplified interface for optimizing unused peripheralsData Movement Subsystem (DMSS)Block Copy DMA (BCDMA)Packet DMA (PKTDMA)Secure Proxy (SEC_PROXY)Ring Accelerator (RINGACC)Security:Secure boot supportedHardware-enforced Root-of-Trust (RoT)Support to switch RoT via backup keySupport for takeover protection, IP protection, and anti-roll back protectionTrusted Execution Environment (TEE) supportedArm TrustZone based TEESecure watchdog/timer/IPCExtensive firewall support for isolationSecure storage supportReplay Protected Memory Block (RPMB) supportSecurity co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for securityCryptographic acceleration supportedSession-aware cryptographic engine with ability to auto-switch key-material based on incoming data streamSupports cryptographic coresAES – 128-/192-/256-Bit key sizesSHA2 – 224-/256-/384-/512-Bit key sizesDRBG with true random number generatorPKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure bootDebugging securitySecure software controlled debug accessSecurity aware debuggingHigh-speed interfaces:1× Integrated Ethernet switch (CPSW3G) supporting:Up to 2 Ethernet portsRMII (10/100)RGMII (10/100/1000)IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTPClause 45 MDIO PHY managementEnergy efficient Ethernet (802.3az)1× PCI-Express Gen2 controller (PCIE)Supports Gen2 operationSupports Single Lane operation1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)Port configurable as USB host,USB device, orUSB Dual-Role deviceUSB device: High-speed (480Mbps), andFull-speed (12Mbps)USB host: SuperSpeed Gen 1 (5Gbps),High-speed (480Mbps),Full-speed (12Mbps), andLow-speed (1.5Mbps)General connectivity:6× Inter-Integrated Circuit (I2C) ports9× configurable Universal Asynchronous Receive/Transmit (UART) modules1× Flash Subsystem (FSS) that can be configured as Octal SPI (OSPI) flash interfaces or one Quad SPI (QSPI)1× 12-Bit Analog-to-Digital Converters (ADC)Up to 4MSPS8× multiplexed analog inputs7× Multichannel Serial Peripheral Interfaces (MCSPI) controllers6× Fast Serial Interface Receiver (FSI_RX) cores2× Fast Serial Interface Transmitter (FSI_TX) cores3× General-Purpose I/O (GPIO) modulesControl interfaces:9× Enhanced Pulse-Width Modulator (EPWM) modules3× Enhanced Capture (ECAP) modules3× Enhanced Quadrature Encoder Pulse (EQEP) modules2× Modular Controller Area Network (MCAN) modules with or without full CAN-FD supportMedia and data storage:2× Multi-Media Card/Secure Digital (MMC/SD/SDIO) interfacesOne 4-bit for SD/SDIO;One 8-bit for eMMCIntegrated analog switch for voltage switching between 3.3V to 1.8V for high-speed cardsPower management:Simplified power sequenceIntegrated SDIO LDO for handling automatic voltage transition for SD interfaceIntegrated voltage supervisor for safety monitoring of over-under voltage conditionsIntegrated power supply glitch detector for detecting fast supply transientsFunctional Safety:Functional Safety-CompliantDeveloped for functional safety applicationsDocumentation available to aid IEC 61508 functional safety system designSystematic capability up to SIL 3Hardware integrity up to SIL 2Safety-related certificationIEC 61508 certification by TÜV SÜDFunctional Safety FeaturesECC or parity on calculation-critical memoriesECC and parity on select internal bus interconnectBuilt-In Self-Test (BIST) for CPU and on-chip RAMError Signaling Module (ESM) with error pinRuntime safety diagnostics, voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engine for memory integrity checksDedicated MCU domain memory, interfaces, and M4F core capable of being isolated from the larger SoC with Freedom From Interference (FFI) featuresSeparate interconnectFirewalls and timeout gasketsDedicated PLLDedicated I/O supplySeparate resetSoC architecture:Supports primary boot from UART, I2C, OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, SD, eMMC, USB, PCIe, and Ethernet interfaces16-nm FinFET technology17.2mm × 17.2mm, 0.8-mm pitch, 441-pin BGA packageProcessor cores:1× Dual 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.0GHzDual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECCEach A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protectionUp to 2× Dual-core Arm Cortex-R5F MCU subsystems at up to 800MHz, integrated for real-time processingDual-core Arm Cortex-R5F supports dual-core and single-core modes32KB ICache, 32KB DCache and 64KB TCM per each R5F core for a total of 256KB TCM with SECDED ECC on all memories1× Single-core Arm Cortex-M4F MCU at up to 400MHz256KB SRAM with SECDED ECCIndustrial subsystem:2× gigabit Industrial Communication Subsystems (PRU_ICSSG)Supports Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and moreBackward compatibility with 10/100Mb PRU_ICSSEach PRU_ICSSG contains:2× Ethernet portsMII (10/100)RGMII (10/100/1000)6 PRU RISC cores per PRU_ICSSG each core having:Instruction RAM with ECCBroadside RAMMultiplier with optional accumulator (MAC)CRC16/32 hardware acceleratorByte swap for Big/Little Endian conversionSUM32 hardware accelerator for UDP checksumTask Manager for preemption supportThree Data RAMs with ECC8 banks of 30 × 32-bit register scratchpad memoryInterrupt controller and task managerTwo 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions18× Sigma-Delta filtersShort circuit logicOver-current logic6× Multi-protocol position encoder interfacesOne Enhanced Capture Module (ECAP)16550-compatible UART with a dedicated 192-MHz clock to support 12-Mbps PROFIBUSMemory subsystem:Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banksEach memory bank can be allocated to a single core to facilitate software task partitioningDDR Subsystem (DDRSS)Supports LPDDR4, DDR4 memory types16-Bit data bus with inline ECCSupports speeds up to 1600MT/s1× General-Purpose Memory Controller (GPMC)16-Bit parallel bus with 133-MHz clock or32-Bit parallel bus with 100-MHz clockError Location Module (ELM) supportSystem on Chip (SoC) Services:Device Management Security Controller (DMSC-L)Centralized SoC system controllerManages system services including initial boot, security, and clock/reset/power managementCommunication with various processing units over message managerSimplified interface for optimizing unused peripheralsData Movement Subsystem (DMSS)Block Copy DMA (BCDMA)Packet DMA (PKTDMA)Secure Proxy (SEC_PROXY)Ring Accelerator (RINGACC)Security:Secure boot supportedHardware-enforced Root-of-Trust (RoT)Support to switch RoT via backup keySupport for takeover protection, IP protection, and anti-roll back protectionTrusted Execution Environment (TEE) supportedArm TrustZone based TEESecure watchdog/timer/IPCExtensive firewall support for isolationSecure storage supportReplay Protected Memory Block (RPMB) supportSecurity co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for securityCryptographic acceleration supportedSession-aware cryptographic engine with ability to auto-switch key-material based on incoming data streamSupports cryptographic coresAES – 128-/192-/256-Bit key sizesSHA2 – 224-/256-/384-/512-Bit key sizesDRBG with true random number generatorPKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure bootDebugging securitySecure software controlled debug accessSecurity aware debuggingHigh-speed interfaces:1× Integrated Ethernet switch (CPSW3G) supporting:Up to 2 Ethernet portsRMII (10/100)RGMII (10/100/1000)IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTPClause 45 MDIO PHY managementEnergy efficient Ethernet (802.3az)1× PCI-Express Gen2 controller (PCIE)Supports Gen2 operationSupports Single Lane operation1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)Port configurable as USB host,USB device, orUSB Dual-Role deviceUSB device: High-speed (480Mbps), andFull-speed (12Mbps)USB host: SuperSpeed Gen 1 (5Gbps),High-speed (480Mbps),Full-speed (12Mbps), andLow-speed (1.5Mbps)General connectivity:6× Inter-Integrated Circuit (I2C) ports9× configurable Universal Asynchronous Receive/Transmit (UART) modules1× Flash Subsystem (FSS) that can be configured as Octal SPI (OSPI) flash interfaces or one Quad SPI (QSPI)1× 12-Bit Analog-to-Digital Converters (ADC)Up to 4MSPS8× multiplexed analog inputs7× Multichannel Serial Peripheral Interfaces (MCSPI) controllers6× Fast Serial Interface Receiver (FSI_RX) cores2× Fast Serial Interface Transmitter (FSI_TX) cores3× General-Purpose I/O (GPIO) modulesControl interfaces:9× Enhanced Pulse-Width Modulator (EPWM) modules3× Enhanced Capture (ECAP) modules3× Enhanced Quadrature Encoder Pulse (EQEP) modules2× Modular Controller Area Network (MCAN) modules with or without full CAN-FD supportMedia and data storage:2× Multi-Media Card/Secure Digital (MMC/SD/SDIO) interfacesOne 4-bit for SD/SDIO;One 8-bit for eMMCIntegrated analog switch for voltage switching between 3.3V to 1.8V for high-speed cardsPower management:Simplified power sequenceIntegrated SDIO LDO for handling automatic voltage transition for SD interfaceIntegrated voltage supervisor for safety monitoring of over-under voltage conditionsIntegrated power supply glitch detector for detecting fast supply transientsFunctional Safety:Functional Safety-CompliantDeveloped for functional safety applicationsDocumentation available to aid IEC 61508 functional safety system designSystematic capability up to SIL 3Hardware integrity up to SIL 2Safety-related certificationIEC 61508 certification by TÜV SÜDFunctional Safety FeaturesECC or parity on calculation-critical memoriesECC and parity on select internal bus interconnectBuilt-In Self-Test (BIST) for CPU and on-chip RAMError Signaling Module (ESM) with error pinRuntime safety diagnostics, voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engine for memory integrity checksDedicated MCU domain memory, interfaces, and M4F core capable of being isolated from the larger SoC with Freedom From Interference (FFI) featuresSeparate interconnectFirewalls and timeout gasketsDedicated PLLDedicated I/O supplySeparate resetSoC architecture:Supports primary boot from UART, I2C, OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, SD, eMMC, USB, PCIe, and Ethernet interfaces16-nm FinFET technology17.2mm × 17.2mm, 0.8-mm pitch, 441-pin BGA package

Description

AM64x is an extension of the Sitara™ Industrial-grade family of heterogeneous Arm® processors. AM64x is built for industrial applications, such as motor drives and Programmable Logic Controllers (PLCs), which require a unique combination of real-time processing and communications with applications processing. AM64x combines two instances of the Sitara device’s gigabit TSN-enabled PRU-ICSSG with up to two Arm® Cortex®-A53 cores, up to four Cortex-R5F MCUs, and a Cortex-M4F MCU. AM64x is architected to provide real-time performance through the high-performance R5Fs, Tightly-Coupled Memory banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM64x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters, and absolute encoder interfaces help enable a number of different architectures found in these systems. The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Real-time (RT) Linux, is provided through TI’s Processor SDK Linux which stays updated to the latest Long Term Support (LTS) Linux kernel, bootloader and Yocto file system on an annual basis. AM64x helps bridge the Linux world with the real-time world by enabling isolation between Linux applications and real-time streams through configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently. The AM64x provides flexible industrial communications capability including full protocol stacks for EtherCAT SubDevice, PROFINET device, EtherNet/IP adapter, and IO-Link Master. The PRU-ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU-ICSSG also enables additional interfaces in the SoC including sigma delta decimation filters and absolute encoder interfaces. Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM64x also supports secure boot. AM64x is an extension of the Sitara™ Industrial-grade family of heterogeneous Arm® processors. AM64x is built for industrial applications, such as motor drives and Programmable Logic Controllers (PLCs), which require a unique combination of real-time processing and communications with applications processing. AM64x combines two instances of the Sitara device’s gigabit TSN-enabled PRU-ICSSG with up to two Arm® Cortex®-A53 cores, up to four Cortex-R5F MCUs, and a Cortex-M4F MCU. AM64x is architected to provide real-time performance through the high-performance R5Fs, Tightly-Coupled Memory banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM64x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters, and absolute encoder interfaces help enable a number of different architectures found in these systems. The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Real-time (RT) Linux, is provided through TI’s Processor SDK Linux which stays updated to the latest Long Term Support (LTS) Linux kernel, bootloader and Yocto file system on an annual basis. AM64x helps bridge the Linux world with the real-time world by enabling isolation between Linux applications and real-time streams through configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently. The AM64x provides flexible industrial communications capability including full protocol stacks for EtherCAT SubDevice, PROFINET device, EtherNet/IP adapter, and IO-Link Master. The PRU-ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU-ICSSG also enables additional interfaces in the SoC including sigma delta decimation filters and absolute encoder interfaces. Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM64x also supports secure boot.