Catalog
Automotive Dual UART With 64-Byte FIFO
Key Features
• Q100 Automotive QualifiedPin Compatible With TL16C2550 With Enhanced Features Provided Through an Improved FIFO RegisterSupports Wide Supply Voltage Range of 1.62 V to 5.5 V3 Mbps (48-MHz Oscillator Input Clock) at 5 V2 Mbps (32-MHz Oscillator Input Clock) at 3.3 V1.5 Mbps (24-MHz Oscillator Input Clock) at 2.5 V1 Mbps (16-MHz Oscillator Input Clock) at 1.8 VCharacterized for Operation from –40°C to 105°C64-Byte Transmit/Receive FIFOSoftware-Selectable Baud-Rate GeneratorProgrammable and Selectable Transmit and Receive FIFO Trigger Levels for DMA, Interrupt Generation, and Software or Hardware Flow ControlSoftware/Hardware Flow ControlProgrammable Xon and Xoff Characters With Optional Xon Any CharacterProgrammable Auto-RTS and Auto-CTS-Modem Control Functions (CTS, RTS, DSR, DTR, RI, and CD)DMA Signaling Capability for Both Received and Transmitted Data on PN PackageRS-485 Mode SupportInfrared Data Association (IrDA) CapabilityProgrammable Sleep ModeProgrammable Serial Interface Characteristics5, 6, 7, or 8-Bit Characters With 1, 1.5, or 2 Stop Bit GenerationEven, Odd, or No Parity Bit Generation and DetectionFalse Start Bit and Line Break DetectionInternal Test and Loopback CapabilitiesSC16C752B and XR16M752 Pin Compatible With Additional EnhancementsQ100 Automotive QualifiedPin Compatible With TL16C2550 With Enhanced Features Provided Through an Improved FIFO RegisterSupports Wide Supply Voltage Range of 1.62 V to 5.5 V3 Mbps (48-MHz Oscillator Input Clock) at 5 V2 Mbps (32-MHz Oscillator Input Clock) at 3.3 V1.5 Mbps (24-MHz Oscillator Input Clock) at 2.5 V1 Mbps (16-MHz Oscillator Input Clock) at 1.8 VCharacterized for Operation from –40°C to 105°C64-Byte Transmit/Receive FIFOSoftware-Selectable Baud-Rate GeneratorProgrammable and Selectable Transmit and Receive FIFO Trigger Levels for DMA, Interrupt Generation, and Software or Hardware Flow ControlSoftware/Hardware Flow ControlProgrammable Xon and Xoff Characters With Optional Xon Any CharacterProgrammable Auto-RTS and Auto-CTS-Modem Control Functions (CTS, RTS, DSR, DTR, RI, and CD)DMA Signaling Capability for Both Received and Transmitted Data on PN PackageRS-485 Mode SupportInfrared Data Association (IrDA) CapabilityProgrammable Sleep ModeProgrammable Serial Interface Characteristics5, 6, 7, or 8-Bit Characters With 1, 1.5, or 2 Stop Bit GenerationEven, Odd, or No Parity Bit Generation and DetectionFalse Start Bit and Line Break DetectionInternal Test and Loopback CapabilitiesSC16C752B and XR16M752 Pin Compatible With Additional Enhancements
Description
AI
The TL16C752CI-Q1 is a dual universal asynchronous receiver transmitter (UART) with 64-byte FIFOs, automatic hardware and software flow control, and data rates up to 3 Mbps. The device offers enhanced features. It has a transmission Character control register (TCR) that stores received FIFO threshold level to start or stop transmission during hardware and software flow control.
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With the FIFO RDY register, the software gets the status of TXRDY or RXRDY for all two ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics. The TL16C752CI-Q1 incorporates the functionality of two UARTs, each UART having its own register set and FIFOs. The two UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is asynchronous communications element (ACE), and these terms are used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C752CI-Q1 device.
The TL16C752CI-Q1 is a dual universal asynchronous receiver transmitter (UART) with 64-byte FIFOs, automatic hardware and software flow control, and data rates up to 3 Mbps. The device offers enhanced features. It has a transmission Character control register (TCR) that stores received FIFO threshold level to start or stop transmission during hardware and software flow control.
All trademarks are the property of their respective owners.
With the FIFO RDY register, the software gets the status of TXRDY or RXRDY for all two ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics. The TL16C752CI-Q1 incorporates the functionality of two UARTs, each UART having its own register set and FIFOs. The two UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is asynchronous communications element (ACE), and these terms are used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C752CI-Q1 device.
