ADS62C15 Series
Dual-Channel, 11-Bit, 125-MSPS Analog-to-Digital Converter (ADC)
Manufacturer: Texas Instruments
Catalog
Dual-Channel, 11-Bit, 125-MSPS Analog-to-Digital Converter (ADC)
| Part | Input Type | Voltage - Supply, Digital [Min] | Voltage - Supply, Digital [Max] | Package / Case | Supplier Device Package | Number of Inputs | Reference Type | Ratio - S/H:ADC | Features | Number of Bits | Voltage - Supply, Analog [Max] | Voltage - Supply, Analog [Min] | Data Interface | Number of A/D Converters | Configuration | Sampling Rate (Per Second) | Architecture | Operating Temperature [Max] | Operating Temperature [Min] | Mounting Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
 Texas Instruments | Differential | 1.65 V | 3.6 V | 64-VFQFN Exposed Pad | 64-VQFN (9x9) | 2 | External Internal | 1:1 | Simultaneous Sampling | 11 | 3.6 V | 3 V | LVDS - Parallel Parallel | 2 | S/H-ADC | 125 M | Pipelined | 85 °C | -40 °C | Surface Mount |
Texas Instruments | Differential | 1.65 V | 3.6 V | 64-VFQFN Exposed Pad | 64-VQFN (9x9) | 2 | External Internal | 1:1 | Simultaneous Sampling | 11 | 3.6 V | 3 V | LVDS - Parallel Parallel | 2 | S/H-ADC | 125 M | Pipelined | 85 °C | -40 °C | Surface Mount |
Texas Instruments | Differential | 1.65 V | 3.6 V | 64-VFQFN Exposed Pad | 64-VQFN (9x9) | 2 | External Internal | 1:1 | Simultaneous Sampling | 11 | 3.6 V | 3 V | LVDS - Parallel Parallel | 2 | S/H-ADC | 125 M | Pipelined | 85 °C | -40 °C | Surface Mount |
Texas Instruments | Differential | 1.65 V | 3.6 V | 64-VFQFN Exposed Pad | 64-VQFN (9x9) | 2 | External Internal | 1:1 | Simultaneous Sampling | 11 | 3.6 V | 3 V | LVDS - Parallel Parallel | 2 | S/H-ADC | 125 M | Pipelined | 85 °C | -40 °C | Surface Mount |
Key Features
• Maximum Sample Rate: 125 MSPS11-Bit Resolution With No Missing Codes82 dBc SFDR at Fin = 117 MHz67 dBFS SNR at Fin = 117 MHz77.5 dBFS SNR at Fin = 117 MHz, 20MHz bandwidthusing technology92 dB CrosstalkParallel CMOS and DDR LVDS Output Options3.5 dB Coarse Gain and Programmable Fine Gainup to 6 dB for SNR/SFDR Trade-OffDigital Processing BlockWith:Offset CorrectionFine Gain Correction, in Steps of 0.05 dBDecimation by 2/4/8Built-in and Custom Programmable 24-Tap Low/High/Band Pass FiltersSupports Sine, LVPECL, LVDS and LVCMOS Clocks andAmplitude Down to 400 mVPPClock Duty Cycle StabilizerInternal Reference; Also Supports External Reference64-QFN Package (9mm × 9mm)Maximum Sample Rate: 125 MSPS11-Bit Resolution With No Missing Codes82 dBc SFDR at Fin = 117 MHz67 dBFS SNR at Fin = 117 MHz77.5 dBFS SNR at Fin = 117 MHz, 20MHz bandwidthusing technology92 dB CrosstalkParallel CMOS and DDR LVDS Output Options3.5 dB Coarse Gain and Programmable Fine Gainup to 6 dB for SNR/SFDR Trade-OffDigital Processing BlockWith:Offset CorrectionFine Gain Correction, in Steps of 0.05 dBDecimation by 2/4/8Built-in and Custom Programmable 24-Tap Low/High/Band Pass FiltersSupports Sine, LVPECL, LVDS and LVCMOS Clocks andAmplitude Down to 400 mVPPClock Duty Cycle StabilizerInternal Reference; Also Supports External Reference64-QFN Package (9mm × 9mm)
Description
AI
ADS62C15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.
ADS62C15 uses proprietary technology that can be used to overcome SNR limitation due to quantization noise (for bandwidths less than Nyquist, Fs/2). It includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.
Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62C15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. The device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).
ADS62C15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.
ADS62C15 uses proprietary technology that can be used to overcome SNR limitation due to quantization noise (for bandwidths less than Nyquist, Fs/2). It includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.
Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62C15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. The device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).