LMK1D1216 Series
16-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer
Manufacturer: Texas Instruments
Catalog
16-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer
Key Features
• High-performance LVDS clock buffer family: up to 2 GHz2:12 differential buffer (LMK1D1212)2:16 differential buffer (LMK1D1216)Supply voltage: 1.71 V to 3.465 VLow additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHzVery low phase noise floor: -164 dBc/Hz (typical)Very low propagation delay: < 575 ps maximumOutput skew: 20 ps maximumHigh-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levelsLVDS reference voltage, V AC_REF, available for capacitive-coupled inputsIndustrial temperature range: –40°C to 105°CPackaged inLMK1D1212: 6-mm × 6-mm, 40-pin VQFN (RHA)LMK1D1216: 7-mm × 7-mm, 48-pin VQFN (RGZ)High-performance LVDS clock buffer family: up to 2 GHz2:12 differential buffer (LMK1D1212)2:16 differential buffer (LMK1D1216)Supply voltage: 1.71 V to 3.465 VLow additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHzVery low phase noise floor: -164 dBc/Hz (typical)Very low propagation delay: < 575 ps maximumOutput skew: 20 ps maximumHigh-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levelsLVDS reference voltage, V AC_REF, available for capacitive-coupled inputsIndustrial temperature range: –40°C to 105°CPackaged inLMK1D1212: 6-mm × 6-mm, 40-pin VQFN (RHA)LMK1D1216: 7-mm × 7-mm, 48-pin VQFN (RGZ)
Description
AI
The LMK1D1212 clock buffer distributes with minimum skew one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11). Similarly, the LMK1D1216 distributes 16 pairs of differential LVDS clock outputs (OUT0 through OUT15). The LMK1D121x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML, or LVCMOS.
The LMK1D121x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.
The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).
The LMK1D1212 clock buffer distributes with minimum skew one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11). Similarly, the LMK1D1216 distributes 16 pairs of differential LVDS clock outputs (OUT0 through OUT15). The LMK1D121x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML, or LVCMOS.
The LMK1D121x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.
The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).
