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SN74ABT16373A-EP

SN74ABT16373A-EP Series

Enhanced Product 16-Bit Transparent D-Type Latches With 3-State Outputs

Manufacturer: Texas Instruments

Catalog

Enhanced Product 16-Bit Transparent D-Type Latches With 3-State Outputs

Key Features

• Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of -55°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product Change NotificationQualification Pedigree(1)Member of the Texas Instruments Widebus™ FamilyState-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power DissipationLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP(Output Ground Bounce) <0.8 V at VCC= 5 V, TA= 25°CHigh-Impedance State During Power Up and Power DownDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoiseFlow-Through Architecture Optimizes PCB LayoutHigh-Drive Outputs (-24-mA IOH, 48-mA IOL)Plastic 300-mil Shrink Small-Outline (DL) Package(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold-compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.Widebus, EPIC-IIB are trademarks of Texas Instruments.Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of -55°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product Change NotificationQualification Pedigree(1)Member of the Texas Instruments Widebus™ FamilyState-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power DissipationLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP(Output Ground Bounce) <0.8 V at VCC= 5 V, TA= 25°CHigh-Impedance State During Power Up and Power DownDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoiseFlow-Through Architecture Optimizes PCB LayoutHigh-Drive Outputs (-24-mA IOH, 48-mA IOL)Plastic 300-mil Shrink Small-Outline (DL) Package(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold-compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.Widebus, EPIC-IIB are trademarks of Texas Instruments.

Description

AI
The SN74ABT16373A-EP is a 16-bit transparent D-type latch with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The SN74ABT16373A-EP is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The SN74ABT16373A-EP can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OEdoes not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74ABT16373A-EP is characterized for operation from -55°C to 125°C. The SN74ABT16373A-EP is a 16-bit transparent D-type latch with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The SN74ABT16373A-EP is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The SN74ABT16373A-EP can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OEdoes not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74ABT16373A-EP is characterized for operation from -55°C to 125°C.