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71V2546

71V2546 Series

3.3V 128Kx36 ZBT Synchronous PipeLined SRAM with 2.5V I/O

Catalog

3.3V 128Kx36 ZBT Synchronous PipeLined SRAM with 2.5V I/O

Description

AI
The 71V2546 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2546 has an on-chip burst counter. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.