NC7SZ374 Series

TinyLogic UHS D-Type Flip-Flop with 3-STATE Output

Catalog

TinyLogic UHS D-Type Flip-Flop with 3-STATE Output

Part	Input Capacitance	Trigger Type	Current - Output High, Low [y]	Current - Output High, Low [x]	Number of Bits per Element	Number of Elements	Package / Case	Function	Output Type	Type	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Max]	Voltage - Supply [Min]	Current - Quiescent (Iq)	Supplier Device Package	Max Propagation Delay @ V, Max CL	Mounting Type
ON Semiconductor NC7SZ374L6X	3 pF	Positive Edge	32 mA	32 mA	1	1	6-UFDFN	Standard	Non-Inverted Tri-State	D-Type	85 °C	-40 °C	5.5 V	1.65 V	1 µA	6-MicroPak	4 ns	Surface Mount
ON Semiconductor NC7SZ374P6X-L22347	3 pF	Positive Edge	32 mA	32 mA	1	1	6-TSSOP SC-88 SOT-363	Standard	Non-Inverted Tri-State	D-Type	85 °C	-40 °C	5.5 V	1.65 V	1 µA	SC-88 SC70-6 SOT-363	4 ns	Surface Mount

Catalog

TinyLogic UHS D-Type Flip-Flop with 3-STATE Output

Key Features

• Space saving SC70 6-lead package

• Ultra small MicroPak™ leadless package

• Ultra High Speed; tPD2.6 ns Typ into 50 pF at 5V VCC

• High Output Drive; ±24 mA at 3V VCC

• Broad VCCOperating Range; 1.65V to 5.5V

• Matches the performance of LCX when operated at 3.3V VCC

• Power down high impedance inputs/output

• Overvoltage tolerant inputs facilitate 5V - 3V translation

• Patented noise/EMI reduction circuitry implemented

Description

The NC7SZ374 is a single positive edge-triggered D-type CMOS Flip-Flop with 3-STATE output from ON Semiconductor's Ultra High Speed Series of TinyLogic® in the space saving SC70 6-lead package. The device is fabricated with advanced CMOS technology to achieve ultra high speed with high output drive while maintaining low static power dissipation over a very broad VCCoperating range. The device is specified to operate over the 1.65V to 5.5V VCCrange. The inputs and output are high impedance when VCCis 0V. Inputs tolerate voltages up to 7V independent of VCCoperating voltage. This single flip-flop will store the state of the D input that meets the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. The output tolerates voltages above VCCin the 3-STATE condition.