Catalog
PCI-to-PCI bridge
Key Features
• Two 32-bit, 66-MHz PCI buses3.3-V core logic with universal PCI interfaces compatiblewith 3.3-V and 5-V PCI signaling environmentsInternal two-tier arbitration for up to nine secondarybus masters and supports an external secondary bus arbiterTen secondary PCI clock outputsIndependent read and write buffers for each directionBurst data transfers with pipeline architecture to maximizedata throughput in both directionsSupports write combing for enhanced data throughputUp to three delayed transactions in both directionsSupports the frame-to-frame delay of only four PCI clocksfrom one bus to anotherBus locking propagationPredictable latency perPCI Local Bus SpecificationArchitecture configurable forPCI Bus Power ManagementInterface SpecificationCompactPCI hot-swap functionalitySecondary bus is driven low during resetVGA/palette memory and I/O decoding optionsAdvanced submicron, low-power CMOS technology208-terminal PDV, 208-terminal PPM, or 257-terminalMicroStar BGA™ packageTwo 32-bit, 66-MHz PCI buses3.3-V core logic with universal PCI interfaces compatiblewith 3.3-V and 5-V PCI signaling environmentsInternal two-tier arbitration for up to nine secondarybus masters and supports an external secondary bus arbiterTen secondary PCI clock outputsIndependent read and write buffers for each directionBurst data transfers with pipeline architecture to maximizedata throughput in both directionsSupports write combing for enhanced data throughputUp to three delayed transactions in both directionsSupports the frame-to-frame delay of only four PCI clocksfrom one bus to anotherBus locking propagationPredictable latency perPCI Local Bus SpecificationArchitecture configurable forPCI Bus Power ManagementInterface SpecificationCompactPCI hot-swap functionalitySecondary bus is driven low during resetVGA/palette memory and I/O decoding optionsAdvanced submicron, low-power CMOS technology208-terminal PDV, 208-terminal PPM, or 257-terminalMicroStar BGA™ package
Description
AI
The Texas Instruments PCI2050B PCI-to-PCI bridge provides a high performance connection path between two peripheral component interconnect (PCI) buses operating at a maximum bus frequency of 66-MHz. Transactions occur between masters on one and targets on another PCI bus, and the PCI2050B bridge allows bridged transactions to occur concurrently on both buses. The bridge supports burst mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently.
The PCI2050B bridge is compliant with thePCI Local Bus Specification, and can be used to overcome the electrical loading limits of 10 devices per PCI bus and one PCI device per extension slot by creating hierarchical buses. The PCI2050B provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with an external bus arbiter.
The CompactPCI™ hot-swap extended PCI capability makes the PCI2050B bridge an ideal solution for multifunction compact PCI cards and adapting single function cards to hot-swap compliance.
The PCI2050B bridge is compliant with thePCI-to-PCI Bridge Specification(Revision 1.1). The PCI2050B bridge provides compliance forPCI Bus Power Management Interface Specification(Revision 1.1). The PCI2050B bridge has been designed to lead the industry in power conservation and data throughput. An advanced CMOS process achieves low system power consumption while operating at PCI clock rates up to 66-MHz.
The Texas Instruments PCI2050B PCI-to-PCI bridge provides a high performance connection path between two peripheral component interconnect (PCI) buses operating at a maximum bus frequency of 66-MHz. Transactions occur between masters on one and targets on another PCI bus, and the PCI2050B bridge allows bridged transactions to occur concurrently on both buses. The bridge supports burst mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently.
The PCI2050B bridge is compliant with thePCI Local Bus Specification, and can be used to overcome the electrical loading limits of 10 devices per PCI bus and one PCI device per extension slot by creating hierarchical buses. The PCI2050B provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with an external bus arbiter.
The CompactPCI™ hot-swap extended PCI capability makes the PCI2050B bridge an ideal solution for multifunction compact PCI cards and adapting single function cards to hot-swap compliance.
The PCI2050B bridge is compliant with thePCI-to-PCI Bridge Specification(Revision 1.1). The PCI2050B bridge provides compliance forPCI Bus Power Management Interface Specification(Revision 1.1). The PCI2050B bridge has been designed to lead the industry in power conservation and data throughput. An advanced CMOS process achieves low system power consumption while operating at PCI clock rates up to 66-MHz.
