Catalog
20-85 MHz 32-Bit Channel Link II Deserializer
Key Features
• Wide Operating Range Embedded Clock SER/DESUp to 32-bit Parallel LVCMOS Data20 to 85 MHz Parallel ClockUp to 2.72 Gbps Application Data PaylodSelectable Serial LVDS Bus WidthDual Lane Mode (20 to 50 MHz)Quad Lane Mode (40 to 85 MHz)Simplified Clocking ArchitectureNo Separate Serial Clock LineNo reference Clock RequiredReceiver Locks to Random DataOn-Chip Signal Conditioning for Robust Serial ConnectivityTransmit Pre-EmphasisData RandomizationDC-Balance EncodingReceive Channel DeskewSupports up to 10m CAT-5 at 2.7 GbpsIntegrated LVDS TerminationsBuilt-in AT-SPEED BIST for End-to-End System TestingAC-Coupled Interconnect for Isolation and Fault Protection> 4KV HBM ESD ProtectionSpace-Saving 64-pin TQFP PackageFull Industrial Temperature Range : -40° to +85°CAll trademarks are the property of their respective owners.Wide Operating Range Embedded Clock SER/DESUp to 32-bit Parallel LVCMOS Data20 to 85 MHz Parallel ClockUp to 2.72 Gbps Application Data PaylodSelectable Serial LVDS Bus WidthDual Lane Mode (20 to 50 MHz)Quad Lane Mode (40 to 85 MHz)Simplified Clocking ArchitectureNo Separate Serial Clock LineNo reference Clock RequiredReceiver Locks to Random DataOn-Chip Signal Conditioning for Robust Serial ConnectivityTransmit Pre-EmphasisData RandomizationDC-Balance EncodingReceive Channel DeskewSupports up to 10m CAT-5 at 2.7 GbpsIntegrated LVDS TerminationsBuilt-in AT-SPEED BIST for End-to-End System TestingAC-Coupled Interconnect for Isolation and Fault Protection> 4KV HBM ESD ProtectionSpace-Saving 64-pin TQFP PackageFull Industrial Temperature Range : -40° to +85°CAll trademarks are the property of their respective owners.
Description
AI
The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or 4 (selectable) embedded clock LVDS serial channels for a data payload rate up to 2.72 Gbps over cables such as CATx, or backplanes FR-4 traces. The companion DS92LV3242 (DES) deserializes the 2 or 4 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus.
On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Pre-emphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing an easy "plug-and-lock" operation.
By embedding the clock in the data payload and including signal conditioning functions, the Channel-Link II SerDes devices reduce trace count, eliminate skew issues, simplify design effort and lower cable/connector cost for a wide variety of video, control and imaging applications. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.
The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or 4 (selectable) embedded clock LVDS serial channels for a data payload rate up to 2.72 Gbps over cables such as CATx, or backplanes FR-4 traces. The companion DS92LV3242 (DES) deserializes the 2 or 4 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus.
On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Pre-emphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing an easy "plug-and-lock" operation.
By embedding the clock in the data payload and including signal conditioning functions, the Channel-Link II SerDes devices reduce trace count, eliminate skew issues, simplify design effort and lower cable/connector cost for a wide variety of video, control and imaging applications. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.
