
LM3881 Series
3 rail simple power sequencer with adjustable time delay
Manufacturer: Texas Instruments
Catalog
3 rail simple power sequencer with adjustable time delay
Key Features
• Easiest Method to Sequence RailsPower-Up and Power-Down ControlTiny FootprintLow Quiescent Current of 80 µAInput Voltage Range of 2.7 V to 5.5 VOutput Invert FeatureTiming Controlled by Small Value ExternalCapacitorEasiest Method to Sequence RailsPower-Up and Power-Down ControlTiny FootprintLow Quiescent Current of 80 µAInput Voltage Range of 2.7 V to 5.5 VOutput Invert FeatureTiming Controlled by Small Value ExternalCapacitor
Description
AI
The LM3881 Simple Power Sequencer offers the easiest method to control power up and power down of multiple power supplies (switching or linear regulators). By staggering the start-up sequence, it is possible to avoid latch conditions or large inrush currents that can affect the reliability of the system.
Available in VSSOP-8 package, the Simple Sequencer contains a precision enable pin and three open-drain output flags. When the LM3881 is enabled, the three output flags will sequentially release, after individual time delays, thus permitting the connected power supplies to start up. The output flags will follow a reverse sequence during power down to avoid latch conditions. Time delays are defined using an external capacitor and the output flag states can be inverted by the user.
The LM3881 Simple Power Sequencer offers the easiest method to control power up and power down of multiple power supplies (switching or linear regulators). By staggering the start-up sequence, it is possible to avoid latch conditions or large inrush currents that can affect the reliability of the system.
Available in VSSOP-8 package, the Simple Sequencer contains a precision enable pin and three open-drain output flags. When the LM3881 is enabled, the three output flags will sequentially release, after individual time delays, thus permitting the connected power supplies to start up. The output flags will follow a reverse sequence during power down to avoid latch conditions. Time delays are defined using an external capacitor and the output flag states can be inverted by the user.